Phase Shift in Timing Reports - 2022.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2022-05-04
Version
2022.1 English

A positive phase shift moves the source clock edge forward, delaying the clock edge. A negative phase shift moves the source clock edge backward. The modification of the clock waveform result in potentially different clock edges being used by the static timing analysis for the source and capture clocks.

In the examples below, clock clkout0 (period 10 ns) is auto-derived by a MMCM.

  • No phase shift
    vivado% set_property CLKOUT0_PHASE 0.000 [get_cells qpll/plle2_adv_inst]
    vivado% report_timing
    ...
    (clock clkout0 rise edge) 0.000 0.000 r
    ...
            MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                   -5.411  5.903 r mmcm_inst/mmcm_adv_inst/CLKOUT0
    ...

    The source clock edge is 0.0 ns.

  • Positive phase shift of 12.0 with PHASESHIFT_MODE=WAVEFORM
    vivado% set_property CLKOUT0_PHASE 12.000 [get_cells qpll/plle2_adv_inst]
    vivado% report_timing
    ...
    (clock clkout0 rise edge) 0.333 0.333 r
    ...
        MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                              -5.411  5.903 r mmcm_inst/mmcm_adv_inst/CLKOUT0
    ...

    The source clock edge is delayed by 0.333 ns (10 ns / 360 * 12.0).

  • Positive phase shift of 12.0 with PHASESHIFT_MODE=LATENCY
    vivado% set_property CLKOUT0_PHASE 12.000 [get_cells qpll/plle2_adv_inst]
    vivado% report_timing
    ...
    (clock clkout0 rise edge) 0.000 0.000 r
    ...
        MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                              -5.078   6.236 r mmcm_inst/mmcm_adv_inst/CLKOUT0 
    ...

    The MMCM insertion delay is increased by 0.333 ns (10 ns / 360 * 12.0). The source clock edge is 0.0 ns.

  • Negative phase shift of -15.0 with PHASESHIFT_MODE=WAVEFORM
    vivado% set_property CLKOUT0_PHASE -15.000 [get_cells qpll/plle2_adv_inst]
    vivado% report_timing
    ...
    (clock clkout0 rise edge) -0.417 -0.417 r
    ...
         MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                               -5.411  5.903 r mmcm_inst/mmcm_adv_inst/CLKOUT0
    ...

    The source clock edge is moved backward by -0.417 ns (10 ns / 360 * -15.0).

  • Negative phase shift of -15.0 with PHASESHIFT_MODE=LATENCY
    vivado% set_property CLKOUT0_PHASE -15.000 [get_cells qpll/plle2_adv_inst]
    vivado% report_timing
    ...
    (clock clkout0 rise edge) 0.000 0.000 r
    ...
         MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                               -5.828   5.486 r mmcm_inst/mmcm_adv_inst/CLKOUT0 
    ...

    The MMCM insertion delay is decreased by 0.417 ns (10 ns / 360 * -15.0). The source clock edge is 0.0 ns.