There is a timing path between the source pin <pin> and the destination pin <pin>. The two latches are <positive|negative> level-sensitive with a 0 ns path requirement.
The 0 ns path requirement is coming from the conservative latch analysis and could
severely impact the runtime due to a time borrowing calculation. Such topology is not
recommended unless there is a multicycle path constraint to adjust the path requirement
to a realistic value (at least half a clock period).