During timing analysis, clock phase-shift can be modeled in two different ways by setting the MMCM/PLL PHASESHIFT_MODE property, as described in the following table.
| PHASESHIFT_MODE Property | Phase-Shift Modeling | Comment |
|---|---|---|
| WAVEFORM | Clock Waveform Modification |
set_multicycle_path
–setup constraints are usually needed to adjust the timing
path requirement on clock-domain-crossing paths from or to the
phase-shifted clock. |
| LATENCY | MMCM/PLL Insertion Delay | No additional multicycle path constraint is needed. |
The default MMCM/PLL clock phase-shift mode varies across Xilinx FPGA families. However, the default mode can be overridden by the user on a per PLL/MMCM basis.
| Technology | Default MMCM/PLL Clock Phase Shift Handling |
|---|---|
| 7 series | Clock waveform modification (WAVEFORM) |
| UltraScale™ | Clock waveform modification (WAVEFORM) |
| UltraScale+™ | MMCM/PLL insertion delay (LATENCY) |
| Versal® ACAP | MMCM/PLL insertion delay (LATENCY) |
CLKOUTx pins and multiple
clocks reach the input pins of the MMCM/PLL, the mode PHASESHIFT_MODE=LATENCY is invalid
and triggers a "Warning Timing 38-437" warning. In such cases, the MMCM/PLL should be
configured to use the mode PHASESHIFT_MODE=WAVEFORM.The use of PHASESHIFT_MODE=LATENCY is particularly convenient when introducing skew between two clocks to meet timing. No additional multicycle path constraint is needed for adjusting the timing path requirement when setting the clock phase-shift to negative, null, or positive.
For legacy designs migrated from 7 series or UltraScale to UltraScale+, when the property PHASESHIFT_MODE is not set on the
MMCM/PLL, the default behavior applies and the MMCM/PLL clock phase-shift is modeled as
delay latency instead of clock edge shift. In this case, all multicycle path constraints
that were specified in the legacy designs to account for a clock phase-shift need to be
reviewed and usually removed. Such constraints can easily be identified by running the
methodology checks (report_methodology). TIMING-31
flags multicycle paths between clocks where one of the clocks is phase-shifted and
generated by a MMCM/PLL with PHASESHIFT_MODE set to
LATENCY.
The Clocking wizard and the High Speed SelectIO™ wizard both provide options to force the clock phase-shift modeling on each MMCM/PLL. The property PHASESHIFT_MODE is automatically saved inside the IP XDC.