This chapter covers techniques that can be used for timing closure. It should be considered in addition to the timing closure techniques described in the UltraFast Design Methodology Timing Closure Quick Reference Guide (UG1292) and UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949).
- Intelligent design runs is an automated timing closure flow that solves complex timing closure issues and requires little user knowledge to use.
- The QoR suggestion object flow enhances QoR automatically for the user by applying properties.
- The ML strategy flow helps the user select optimal tool options for a given design.
- Floorplanning is a complex technique that can guide the placer to improve placer results that can result in improved timing paths and congestion.
- Determining if a design has hold issues can be a key part in determining a timing closure strategy. This section describes how to diagnose if hold is an issue.