Timing Paths Example - 2022.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
UG906
Release Date
2022-05-04
Version
2022.1 English

The following figure shows the paths described above. In this example, the design clock CLK0 can be used as the board clock for both DIN and DOUT delay constraints.

Figure 1. Timing Paths Example