Performing NoC Quality of Service Analysis in Versal Devices - 2022.1 English

The Quality of Service (QoS) Report in Vivado® compares the estimated QoS from the current Network on Chip (NoC) solution generated by the NoC Compiler to the QoS Requirements specified in the AXI NoC IP and/or the AXI4-Stream NoC IP. If at any time the NoC solution becomes out-of-date, it is required to call the NoC Compiler and generate a new NoC solution to update the QoS Report. The QoS Report will show in its banner that it is out-of-date (see the following figure). Clicking the Update link will call the NoC Compiler to regenerate the NoC solution.

Figure 1. Vivado NoC QoS Report that is out-of-date

Actions that can cause the NoC solution to become out-of-date include:

• In IP integrator:
  • Updates to the AXI NoC IP QoS Requirements in IPI
  • Changes to the IPI Block Design
  • Changes to the NoC Master Unit/NoC Slave Unit (NMU/NSU) assignments in the NoC view
• In Implementation Tools/Flow:
  • Unplacing NMU/NSU instances
  • XDC physical constraints impacting NMU/NSU placement
  • Changes to logical net connections to NMU/NSU

  For each connection specified in the NoC, the NoC QoS report reports the following information for both Read and Write Transactions:

• Traffic Class: The traffic class specified on the NoC in IP integrator for the connection
• Bandwidth Required: The bandwidth specified in MegaBytes per second on the NoC IP integrator for the connection
• Bandwidth Estimate: The bandwidth estimated in MegaBytes per second by the NoC Compiler for the current NoC solution
• Latency Estimate: The structural latency estimated in NoC Clock Cycles by the NoC Compiler for the current NoC solution
  Important: There are two very important items to note for the Latency Estimate in the QoS Report. The Latency Estimate is a structural latency, not a dynamic latency. It reports the minimum round-trip time for a transaction. The Latency Estimate is measured in NoC Clock Cycles in the QoS report whereas the Xilinx Performance Traffic Generator IP reports Latency in AXI Clock Cycles in simulation. Due to the structural estimates of the QoS Report in Vivado, it is required that your design be validated with actual traffic stimulus for design signoff.