In the simplified Fanout example shown in the following figure, the source flip-flop drives a net that is synchronized three times in the clk_b domain highlighted in red. This structure is not recommended as it can lead to data coherency issues in the destination clock domain because the latency through the synchronizers is bounded but not cycle-accurate.
Figure 1. Simplified Fanout Example
Note: A fanout of N to N different clock domains is not a CDC problem and does not trigger a CDC-11 violation. Refer to the section Asynchronous Reset Synchronizer for examples of safe fanout on reset signal.