Clock Phase Shift - 2022.1 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2022.1 English

A clock phase-shift corresponds to a delayed clock waveform with respect to a reference clock due to special hardware in the clock path. In Xilinx FPGAs, clock phase-shift is usually introduced by the MMCM or PLL primitives, when their output clock property CLKOUT*_PHASE is non-zero.