link_design - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID

UG835

Release Date

2022-05-05

Version

2022.1 English

Open a netlist design

Syntax

link_design [‑name <arg>] [‑part <arg>] [‑constrset <arg>] [‑top <arg>]
    [‑mode <arg>] [‑pr_config <arg>] [‑reconfig_partitions <args>]
    [‑partitions <args>] [‑ignore_timing] [‑quiet] [‑verbose]

Returns

Design object

Usage

Name	Description
`[-name]`	Design name
`[-part]`	Target part
`[-constrset]`	Constraint fileset to use
`[-top]`	Specify the top module name when the structural netlist is Verilog
`[-mode]`	The design mode. Values: default, out_of_context Default: default
`[-pr_config]`	PR Configuration to apply while opening the design
`[-reconfig_partitions]`	List of reconfigurable partitions to load while opening the design
`[-partitions]`	List of partitions to load while opening the design
`[-ignore_timing]`	open a netlist design without the timing constraints.
`[-quiet]`	Ignore command errors
`[-verbose]`	Suspend message limits during command execution

Description

Opens a new or existing netlist design, linking the netlist files and constraints with the target part to create the design. This command is intended for use with netlist source files, such as files generated by third party synthesis tools, or Vivado® synthesis through the synth_design command.

The DESIGN_MODE property for the current source fileset must be defined as GateLvl in order to open a netlist design. If not, you will get the following error:

ERROR: The design mode of 'sources_1' must be GateLvl.

The -top switch is required for third-party synthesis designs. The netlist for the design must be rooted in a specific module. For project-based designs you can specify the TOP property on the project. However, in non-project mode, you must use the -top option for the link_design command.

For project based designs with RTL source files, use launch_runs to launch synthesis or implementation, and then use the open_run command to open the design.

For non-project based designs, use the open_checkpoint command to open a checkpoint into memory, opening the design in Non-Project Mode. Refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information on Project Mode and Non-Project Mode.

Arguments

-name <arg> - (Optional) This is the name assigned to the netlist design when it is opened by the Vivado® tool. This name is for reference purposes, and has nothing to do with the top-level of the design or any logic contained within.

-part <arg> - (Optional) The Xilinx® device to use when creating a new design. If the part is not specified the default part will be used.

-constrset <arg> - (Optional) The name of the constraint fileset to use when opening the design.

Note: The -constrset argument must refer to a constraint fileset that exists. It cannot be used to create a new fileset. Use create_fileset for that purpose.

-top <arg> - (Optional) The name of the top module of the design hierarchy of the netlist.

Important: When specifying -top with an EDIF netlist-based design, or design checkpoint (DCP) file, the name of the top-level cell must match the top-level cell defined in the EDIF or DCP file.

-mode [ default | out_of_context ] - (Optional) If you have synthesized a block, and disabled IO buffer insertion, you can load the resulting EDIF into the Vivado Design Suite using -mode out_of_context. This enables implementation of the module without IO buffers, prevents optimization due to unconnected inputs or outputs, and adjusts DRC rules appropriately for the design. Refer to the Vivado Design Suite User Guide: Hierarchical Design (UG905) for more information.

-pr_config <arg> - (Optional) For the Partial Reconfiguration (PR) project-based design flow, this option specifies the PR Configuration to apply while opening the design. For PR designs, the create_pr_configuration command lets you associate a Reconfigurable Module (RM) with each Partition Definition in the design. This option tells the Vivado tool to link the design checkpoint files for the RMs into the design. See the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) for more information.

-reconfig_partitions <args> - (Optional) Specify a list of reconfigurable partitions to load while opening the design. The specified reconfigurable partitions are marked with the HD.RECONFIGURABLE property for proper handling in the design.

-partitions <args> - (Optional) List of hierarchical design partitions to load while opening the design. Hierarchical design partitions are marked with the HD.PARTITION property. See the Vivado Design Suite User Guide: Hierarchical Design (UG905) for more information.

-ignore_timing - (Optional) open a netlist design without the timing constraints. This can be used to quickly open a design for evaluation, separate from the timing constraints.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.

Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.

-verbose - (Optional) Temporarily override any message limits and return all messages from this command.

Note: Message limits can be defined with the set_msg_config command.

Examples

The following creates a new netlist design called Net1:

link_design -name Net1

Note: The default source set, constraint set, and part will be used in this example.

The following example opens a netlist design called Net1, and specifies the constraint set to be used:

link_design -name Net1 -constrset con1