Tcl Commands Listed by Category - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2022-05-05
Version
2022.1 English

Bitgen:

Configuration:

Hardware:

add_hw_hbm_pc add_hw_probe_enum boot_hw_device
close_hw_manager close_hw_target commit_hw_hbm
commit_hw_mig commit_hw_sio commit_hw_sysmon
commit_hw_vio config_hw_sio_gts connect_hw_server
create_hw_axi_txn create_hw_bitstream create_hw_cfgmem
create_hw_device create_hw_probe create_hw_sio_link
create_hw_sio_linkgroup create_hw_sio_scan create_hw_sio_sweep
create_hw_target current_hw_cfgmem current_hw_device
current_hw_ila current_hw_ila_data current_hw_server
current_hw_target delete_hw_axi_txn delete_hw_bitstream
delete_hw_cfgmem delete_hw_probe delete_hw_target
detect_hw_sio_links disconnect_hw_server display_hw_ila_data
display_hw_sio_scan execute_hw_svf get_cfgmem_parts
get_hw_axi_txns get_hw_axis get_hw_cfgmems
get_hw_ddrmcs get_hw_devices get_hw_hbmmcs
get_hw_hbms get_hw_ila_datas get_hw_ilas
get_hw_migs get_hw_pcies get_hw_probes
get_hw_servers get_hw_sio_commons get_hw_sio_gtgroups
get_hw_sio_gts get_hw_sio_iberts get_hw_sio_linkgroups
get_hw_sio_links get_hw_sio_plls get_hw_sio_rxs
get_hw_sio_scans get_hw_sio_sweeps get_hw_sio_txs
get_hw_softmcs get_hw_sysmon_reg get_hw_sysmons
get_hw_targets get_hw_vios list_hw_samples
open_hw_manager open_hw_target pause_hw_hbm_amon
program_hw_cfgmem program_hw_devices read_hw_ila_data
read_hw_sio_scan read_hw_sio_sweep readback_hw_cfgmem
readback_hw_device refresh_hw_axi refresh_hw_ddrmc
refresh_hw_device refresh_hw_hbm refresh_hw_hbmmc
refresh_hw_mig refresh_hw_pcie refresh_hw_server
refresh_hw_sio refresh_hw_softmc refresh_hw_sysmon
refresh_hw_target refresh_hw_vio remove_hw_hbm_pc
remove_hw_probe_enum remove_hw_sio_link remove_hw_sio_linkgroup
remove_hw_sio_scan remove_hw_sio_sweep report_hw_axi_txn
report_hw_ddrmc report_hw_mig report_hw_pcie
report_hw_softmc report_hw_targets reset_hw_axi
reset_hw_ila reset_hw_pcie reset_hw_vio_activity
reset_hw_vio_outputs resume_hw_hbm_amon run_hw_axi
run_hw_hbm_amon run_hw_ila run_hw_sio_scan
run_hw_sio_sweep run_state_hw_jtag runtest_hw_jtag
scan_dr_hw_jtag scan_ir_hw_jtag set_hw_sysmon_reg
stop_hw_hbm_amon stop_hw_sio_scan stop_hw_sio_sweep
update_hw_firmware update_hw_gpio upload_hw_ila_data
verify_hw_devices wait_on_hw_ila wait_on_hw_sio_scan
wait_on_hw_sio_sweep write_hw_ila_data write_hw_sio_scan
write_hw_sio_sweep write_hw_svf  

Lint:

Memory Initialization:

Object:

add_drc_checks apply_board_connection can_resolve_reference
config_ip_cache create_drc_check create_drc_ruledeck
create_partition_def create_pr_configuration create_reconfig_module
create_report_config create_waiver current_board
current_board_part current_pr_configuration delete_drc_check
delete_drc_ruledeck delete_hw_bitstream delete_qor_suggestions
delete_report_configs delete_waivers filter
find_routing_path generate_ml_strategies generate_reports
get_bel_pins get_bels get_board_bus_nets
get_board_buses get_board_component_interfaces get_board_component_modes
get_board_component_pins get_board_components get_board_interface_ports
get_board_ip_preferences get_board_jumpers get_board_parameters
get_board_part_interfaces get_board_part_pins get_board_parts
get_boards get_cdc_violations get_cells
get_cfgmem_parts get_clock_regions get_clocks
get_constant_paths get_dashboard_gadgets get_debug_cores
get_debug_ports get_designs get_drc_checks
get_drc_ruledecks get_drc_violations get_files
get_filesets get_generated_clocks get_highlighted_objects
get_hw_axi_txns get_hw_axis get_hw_cfgmems
get_hw_ddrmcs get_hw_devices get_hw_hbmmcs
get_hw_hbms get_hw_ila_datas get_hw_ilas
get_hw_migs get_hw_pcies get_hw_probes
get_hw_servers get_hw_sio_commons get_hw_sio_gtgroups
get_hw_sio_gts get_hw_sio_iberts get_hw_sio_linkgroups
get_hw_sio_links get_hw_sio_plls get_hw_sio_rxs
get_hw_sio_scans get_hw_sio_sweeps get_hw_sio_txs
get_hw_softmcs get_hw_sysmons get_hw_targets
get_hw_vios get_interfaces get_io_standards
get_iobanks get_ip_upgrade_results get_ipdefs
get_ips get_lib_cells get_lib_pins
get_libs get_macros get_marked_objects
get_methodology_checks get_methodology_violations get_net_delays
get_nets get_nodes get_package_pins
get_partition_defs get_parts get_path_groups
get_pblocks get_pins get_pips
get_pkgpin_bytegroups get_pkgpin_nibbles get_ports
get_pr_configurations get_primitives get_projects
get_property get_qor_suggestions get_reconfig_modules
get_report_configs get_runs get_selected_objects
get_site_pins get_site_pips get_sites
get_slrs get_speed_models get_tiles
get_timing_arcs get_timing_paths get_waivers
get_wires list_hw_samples list_property
list_property_value remove_drc_checks report_property
report_qor_suggestions report_waivers reset_drc_check
reset_methodology_check reset_property run_state_hw_jtag
runtest_hw_jtag scan_dr_hw_jtag scan_ir_hw_jtag
set_property validate_board_files write_ip_tcl
write_waivers    

synthesis:

SysGen:

make_wrapper    

vivado_preferences:

XDC:

add_cells_to_pblock add_to_power_rail all_clocks
all_cpus all_dsps all_fanin
all_fanout all_ffs all_hsios
all_inputs all_latches all_outputs
all_rams all_registers connect_debug_cores
connect_debug_port create_clock create_debug_core
create_debug_port create_generated_clock create_macro
create_pblock create_power_rail create_property
create_waiver current_design current_instance
delete_macros delete_pblocks delete_power_rails
filter get_bel_pins get_bels
get_cells get_clocks get_debug_cores
get_debug_ports get_generated_clocks get_hierarchy_separator
get_iobanks get_macros get_nets
get_nodes get_package_pins get_path_groups
get_pblocks get_pins get_pips
get_pkgpin_bytegroups get_pkgpin_nibbles get_ports
get_power_rails get_property get_site_pins
get_site_pips get_sites get_slrs
get_speed_models get_tiles get_timing_arcs
get_wires group_path make_diff_pair_ports
remove_cells_from_pblock remove_from_power_rail reset_operating_conditions
reset_switching_activity resize_pblock set_bus_skew
set_case_analysis set_clock_groups set_clock_latency
set_clock_sense set_clock_uncertainty set_data_check
set_disable_timing set_external_delay set_false_path
set_hierarchy_separator set_input_delay set_input_jitter
set_load set_logic_dc set_logic_one
set_logic_unconnected set_logic_zero set_max_delay
set_max_time_borrow set_min_delay set_multicycle_path
set_operating_conditions set_output_delay set_package_pin_val
set_power_opt set_propagated_clock set_property
set_switching_activity set_system_jitter set_units
update_macro