Generate target data for the specified source
Syntax
generate_target [‑force] [‑quiet] [‑verbose] <name> <objects>
Usage
Name | Description |
---|---|
[-force]
|
Force target data regeneration |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
<name>
|
List of targets to be generated, or 'all' to generate all supported targets |
<objects>
|
The objects for which data needs to be generated |
Categories
Description
This command generates target data for the specified IP objects (get_ips
) or source file for IP cores (.xci and .xco), DSP modules (.slx or .mdl), or block designs (.bd). The target data that is generated are the files necessary to support the IP or block design through the FPGA design flow.
The instantiation template, synthesis netlist, and simulation netlist are standard targets. However, each IP in the catalog may also support its own set of targets. You can view the available targets on an object by examining the SUPPORTED_TARGETS property, or you can use the list_targets
command to list the targets for design source file.
Arguments
-force
- (Optional) Force target data regeneration, and overwrite any existing target data files. Without -force
, the tool will not regenerate any target data that is up-to-date.
-quiet
- (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose
- (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config
command.<name>
- (Required) The names of the types of target data to create for the specified source. The specific targets supported by an IP core are listed in the SUPPORTED_TARGETS property on the object. You can query this property to see which targets a specific object supports. Standard values are:
-
all
- Generate all targets for the specified IP or file, except the example project.Note: You can generate an example project for an IP core using theopen_example_project
command. -
instantiation_template
- Generate the Instantiation template used to add the RTL module definition for the IP core into the current design. The instantiation template can be copied into any desired level of the design hierarchy. -
synthesis
- Synthesis targets deliver HDL files that are used during synthesis for native IP, or deliver a synthesized netlist file (DCP) generated by Vivado® synthesis. -
simulation
- Simulation targets deliver HDL files that are used in simulation. -
implementation
- Implementation generates the necessary data for implementing the IP core, DSP module, or Embedded Processor in the current design.
<objects>
- (Required) The objects to generate the target from. Supported objects can include IP core objects (get_ips
), or the source files (.xci or .xco), block design files (.bd) from IP integrator, and DSP modules (.slx or .mdl) imported from System Generator.
get_files
to specify a file object, rather than specifying a file name.Examples
generate_target changelog [get_ips] -force
generate_target {instantiation_template synthesis} [get_ips]
-force
option means that only out-of-date targets will be regenerated.generate_target all \
[get_files C:/Data/project_mb/project_mb.srcs/sources_1/bd/base_mb/base_mb.bd]
get_ips
is not supported to generate targets for individual IP within block designs. The tool will return an error.get_property SUPPORTED_TARGETS [get_ips blk_mem*]
open_example_project -dir C:/Data/examples -force [get_ips blk_mem*]