synth_design - 2022.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)
Document ID
UG835
Release Date
2022-05-05
Version
2022.1 English

Synthesize a design using Vivado Synthesis and open that design

Syntax

synth_design [‑name <arg>] [‑part <arg>] [‑constrset <arg>] [‑top <arg>]
    [‑include_dirs <args>] [‑generic <args>] [‑verilog_define <args>]
    [‑flatten_hierarchy <arg>] [‑gated_clock_conversion <arg>]
    [‑directive <arg>] [‑rtl] [‑lint] [‑bufg <arg>] [‑no_lc]
    [‑shreg_min_size <arg>] [‑mode <arg>] [‑fsm_extraction <arg>]
    [‑rtl_skip_mlo] [‑rtl_skip_ip] [‑rtl_skip_constraints]
    [‑srl_style <arg>] [‑keep_equivalent_registers]
    [‑resource_sharing <arg>] [‑cascade_dsp <arg>]
    [‑control_set_opt_threshold <arg>] [‑incremental_mode <arg>]
    [‑max_bram <arg>] [‑max_uram <arg>] [‑max_dsp <arg>]
    [‑max_bram_cascade_height <arg>] [‑max_uram_cascade_height <arg>]
    [‑retiming] [‑no_retiming] [‑no_srlextract] [‑assert]
    [‑no_timing_driven] [‑sfcu] [‑debug_log] [‑quiet] [‑verbose]

Returns

Design object

Usage

Name Description
[-name] Design name
[-part] Target part
[-constrset] Constraint fileset to use
[-top] Specify the top module name
[-include_dirs] Specify verilog search directories
[-generic] Specify generic parameters. Syntax: -generic <name>=<value> -generic <name>=<value> ...
[-verilog_define] Specify verilog defines. Syntax: -verilog_define <macro_name>[=<macro_text>] -verilog_define <macro_name>[=<macro_text>] ...
[-flatten_hierarchy] Flatten hierarchy during LUT mapping. Values: full, none, rebuilt Default: rebuilt
[-gated_clock_conversion] Convert clock gating logic to flop enable. Values: off, on, auto Default: off
[-directive] Synthesis directive. Values: default, RuntimeOptimized, AreaOptimized_high, AreaOptimized_medium, AlternateRoutability, AreaMapLargeShiftRegToBRAM, AreaMultThresholdDSP, FewerCarryChains, PerformanceOptimized, LogicCompaction, PowerOptimized_high, PowerOptimized_medium Default: default
[-rtl] Elaborate and open an rtl design
[-lint] Run RTL Linter on source files. Recommended to run before RTL simulation and synthesis to identify potential issues at early design cycle.
[-bufg] Max number of global clock buffers used by synthesis Default: 12
[-no_lc] Disable LUT combining. Do not allow combining LUT pairs into single dual output LUTs.
[-shreg_min_size] Minimum length for chain of registers to be mapped onto SRL Default: 3
[-mode] The design mode. Values: default, out_of_context Default: default
[-fsm_extraction] FSM Extraction Encoding. Values: off, one_hot, sequential, johnson, gray, user_encoding, auto Default: auto
[-rtl_skip_mlo] Skip mandatory logic optimization for RTL elaboration of the design; requires -rtl option.
[-rtl_skip_ip] Exclude subdesign checkpoints in the RTL elaboration of the design; requires -rtl option.
[-rtl_skip_constraints] Do not load and validate constraints against elaborated design; requires -rtl option.
[-srl_style] Static SRL Implementation Style. Values: register, srl, srl_reg, reg_srl, reg_srl_reg
[-keep_equivalent_registers] Prevents registers sourced by the same logic from being merged. (Note that the merging can otherwise be prevented using the synthesis KEEP attribute)
[-resource_sharing] Sharing arithmetic operators. Value: auto, on, off Default: auto
[-cascade_dsp] Controls how adders summing DSP block outputs will be implemented. Value: auto, tree, force Default: auto
[-control_set_opt_threshold] Threshold for synchronous control set optimization to lower number of control sets. Valid values are 'auto' and non-negative integers. The higher the number, the more control set optimization will be performed and fewer control sets will result. To disable control set optimization completely, set to 0. Default: auto
[-incremental_mode] Mode of incremental synthesis (aggressive/default/off/quick) Default: default
[-max_bram] Maximum number of block RAM allowed in design. (Note -1 means that the tool will choose the max number allowed for the part in question) Default: -1
[-max_uram] Maximum number of Ultra RAM blocks allowed in design. (Note -1 means that the tool will choose the max number allowed for the part in question) Default: -1
[-max_dsp] Maximum number of block DSP allowed in design. (Note -1 means that the tool will choose the max number allowed for the part in question) Default: -1
[-max_bram_cascade_height] Controls the maximum number of BRAM that can be cascaded by the tool. (Note -1 means that the tool will choose the max number allowed for the part in question) Default: -1
[-max_uram_cascade_height] Controls the maximum number of URAM that can be cascaded by the tool. (Note -1 means that the tool will choose the max number allowed for the part in question) Default: -1
[-retiming] Seeks to improve circuit performance for intra-clock sequential paths by automatically moving registers (register balancing) across combinatorial gates or LUTs. It maintains the original behavior and latency of the circuit and does not require changes to the RTL sources.
[-no_retiming] Disable -retiming option. Do not run retiming
[-no_srlextract] Prevents the extraction of shift registers so that they get implemented as simple registers
[-assert] Enable VHDL assert statements to be evaluated. A severity level of failure will stop the synthesis flow and produce an error.
[-no_timing_driven] Do not run in timing driven mode
[-sfcu] Run in single-file compilation unit mode
[-debug_log] Print detailed log files for debugging
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Tools

Description

Directly launches the Vivado® synthesis engine to compile and synthesize a design in either Project Mode or Non-Project Mode in the Vivado Design Suite. Refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for a complete description of Project Mode and Non-Project Mode.

Vivado synthesis can be launched directly with the synth_design command in the Non-Project Mode of the Vivado Design Suite.
Tip: The synth_design can be multi-threaded to speed the process. Refer to the set_param command for more information on setting the general.maxThreads parameter.

In Project Mode, synthesis should be launched from an existing synthesis run created with the create_run command. The run is launched using the launch_runs command, and this in turn calls synth_design for Vivado synthesis.

You can also use the synth_design command to elaborate RTL source files, and open an elaborated design: 
synth_design -rtl -name rtl_1

This command returns a transcript of the synthesis process, or returns an error if it fails.

Arguments

-name <arg> - (Optional) This is the name assigned to the synthesized design when it is opened by the Vivado tool after synthesis has completed. This name is for reference purposes, and has nothing to do with the top-level of the design or any logic contained within.

-part <arg> - (Optional) The target Xilinx® device to use for the design. If the part is not specified the default part assigned to the project will be used.

-constrset <arg> - (Optional) The name of the XDC constraints to use when synthesizing the design. Vivado synthesis requires the use of XDC, and does not support UCF. The -constrset argument must refer to a constraint fileset that exists. It cannot be used to create a new fileset. Use the create_fileset command for that purpose.

-top <arg> - (Optional) The top module of the design hierarchy.
Important: If you use the find_top command to define the -top option, be sure to specify only one top if find_top returns multiple prospects. See the examples below.
-include_dirs <args> - (Optional) The directories to search for Verilog `include files. You can specify multiple directories by creating a list to contain them: 
-include_dirs {C:/data/include1 C:/data/include2}
-generic <name>=<value> - (Optional) The value of a VHDL generic entity, or of a Verilog parameter. The -generic option can be used to override the assigned values of parameters in the RTL design sources. However it can only override parameters at the top level of the design. The parameters of lower-level modules can only be overridden at the time of instantiation and not by the -generic option. The syntax for the -generic argument is <name>=<value>, specifying the name of the generic or parameter, and the value to be assigned. Repeat the -generic option multiple times in the synth_design command for each generic or parameter value to be defined: 
synth_design -generic width=32 -generic depth=512 ...
Important: When specifying binary values for boolean or std_logic VHDL generic types, you must specify the value using the Verilog bit format, rather than standard VHDL format: 
0 = 1'b0
01010000 = 8'b01010000
-verilog_define <name>=<text> - (Optional) Set values for Verilog `define, and `ifdef, statements. The syntax for the -verilog_define argument is <name>=<text>, specifying the name of the define directive, and the value to be assigned. The argument can be reused multiple times in a single synth_design command. 
synth_design -verilog_define <name>=<value> -verilog_define <name>=<value> ...
-flatten_hierarchy <arg> - (Optional) Flatten the hierarchy of the design during LUT mapping. The valid values are:
  • rebuilt - This will attempt to rebuild the original hierarchy of the RTL design after synthesis has completed. This is the default setting.
  • full - Flatten the hierarchy of the design.
  • none - Do not flatten the hierarchy of the design. This will preserve the hierarchy of the design, but will also limit the design optimization that can be performed by the synthesis tool.
-gated_clock_conversion <arg> - (Optional) Convert clock gating logic to use the flop enable pins when available. This optimization can eliminate logic and simplify the netlist. Refer to the GATED_CLOCK property in the Vivado Design Suite User Guide: Synthesis (UG901) for more information. Valid values for this option are:
  • off - Disables the conversion of clock gating logic during synthesis, regardless of the use of the GATED_CLOCK property in the RTL design.
  • on - Converts clock gating logic based on the use of the GATED_CLOCK property in the RTL design.
  • auto - lets Vivado synthesis perform gated clock conversion if either the GATED_CLOCK property is present in the RTL, or if the Vivado tool detects a gate with a valid clock constraint.
-directive <arg> - (Optional) Direct synthesis to achieve specific design objectives. Only one directive can be specified for a single synth_design command, and values are case-sensitive. Valid values are:
  • default - Run the default synthesis process.
  • runtimeoptimized - Perform fewer timing optimizations and eliminate some RTL optimizations to reduce synthesis run time.
  • AreaOptimized_high - Perform general area optimizations including AreaMapLargeShiftRegToBRAM, AreaThresholdUseDSP directives.
  • AreaOptimized_medium - Perform general area optimizations including forcing ternary adder implementation, applying new thresholds for use of carry chain in comparators, and implementing area optimized multiplexers.
  • AlternateRoutability - Algorithms to improve routability with reduced use of MUXFs and CARRYs.
  • AreaMapLargeShiftRegToBRAM - Detects large shift registers and implements them using dedicated blocks of RAM.
  • AreaMultThresholdDSP - Lower threshold for dedicated DSP block inference for packing multipliers.
  • FewerCarryChains - Higher operand size threshold to use LUTs instead of the carry chain.
  • PerformanceOptimized - Perform general timing optimizations including logic level reduction at the expense of area.
  • LogicCompaction – Configure LUTs and Carry chains for multipliers in a way that makes it easier for the placer to pack these structures into small areas.

-rtl - (Optional) Elaborate the HDL source files and open the RTL design. In designs that use out-of-context (OOC) modules, such as IP from the Xilinx® IP catalog, the Vivado Design Suite will import synthesized design checkpoints (DCP) for the OOC modules in the design, and import associated constraint files (XDC) into the elaborated design. However, you can disable the default behavior using the -rtl_skip_ip and -rtl_skip_constraints options.

-lint - Run RTL Linter on source files against various rules. The following are the supported rules.
  • ASSIGN-1(arithmetic overlfow)
  • ASSIGN-2(mixed operand signedness)
  • ASSIGN-3(shift overflow)
  • ASSIGN-4(unused scalar)
  • ASSIGN-5(bit in array not set)
  • ASSIGN-6(bit in array not used)
  • ASSIGN-7(mult-assign/multi-driver)
  • QOR-1(arithmetic operator not mergeable)
  • INFER-1(inferred latch)
  • INFER-2(incomplete case statement)
  • INFER-3(case equality)
  • CLOCK-1(module using both clock edges)
  • RESET-1(mixed asyncreset)
  • RESET-2(missing async reset logic)
Create_waiver -type LINT can be used to waive rules or individual linter warnings. For example, 
create_waiver -type LINT -id ASSIGN-3 -description {waive all warnings from ASSIGN-3 check}
-rtl_skip_ip - (Optional) This option requires the use of the -rtl option. When elaborating the RTL design, this option causes the Vivado Design Suite to skip loading the DCP files for OOC modules in the design, and instead load a stub file to treat the OOC modules as black boxes. This can significantly speed elaboration of the design.
Tip: An OOC synthesis run will be needed in either case to generate the DCP file that is loaded during elaboration, or to generate the stub file needed for the black box.

-rtl_skip_constraints - (Optional) This option requires the use of the -rtl option. When elaborating the RTL design, this option causes the Vivado Design Suite to skip loading any design constraints (XDC) into the elaborated design. This can significantly speed elaboration of the design.

-bufg <arg> - (Optional) Specify the maximum number of global clock buffers to be used on clock nets during synthesis. Specified as a value >= 1, which should not exceed the BUFG count on the target device. The default value is 12.
Tip: Vivado synthesis infers up to the number of BUFGs specified, including those instantiated in the RTL source. For example, with the default setting of -bufg 12, if there are three BUFGs instantiated in the RTL, the tool infers up to nine more for a total of 12.

-no_lc - (Optional) Disable the default LUT combining feature of Vivado synthesis.

-shreg_min_size <arg> - (Optional) Specified as an integer, this is the minimum length for a chain of registers to be mapped onto SRL. The default is three.

-mode [ default | out_of_context ] - (Optional) Out of Context mode specifies the synthesis of an IP module, or block module, for use in an out-of-context design flow. This mode turns off I/O buffer insertion for the module, and marks the module as OOC, to facilitate its use in the tool flow. The block can also be implemented for analysis purposes. Refer to the Vivado Design Suite User Guide: Designing with IP (UG896) or the Vivado Design Suite User Guide: Hierarchical Design (UG905) for more information.

-fsm_extraction <arg> - (Optional) Finite state machine (FSM) encoding is automatic (auto) in Vivado synthesis by default. This option enables state machine identification and specifies the type of encoding that should be applied. Valid values are: off, one_hot, sequential, johnson, gray, auto. Automatic encoding (auto) allows the tool to choose the best encoding for each state machine identified. In this case, the tool may use different encoding styles for different FSMs in the same design.
Note: Use -fsm_extraction off to disable finite state machine extraction in Vivado synthesis. This will override the FSM_ENCODING property when specified.

-keep_equivalent_registers - (Optional) Works like the KEEP property to prevent the merging of registers during optimization.

-resource_sharing <arg> - (Optional) Share arithmetic operators like adders or subtractors between different signals, rather than creating new operators. This can result in better area usage when it is turned on. Valid values are: auto, on, off. The default is auto.

-cascade_dsp [ auto | tree | force ] - (Optional) Specifies how to implement adders that add DSP block outputs. Valid values include auto, tree, force. The default setting is auto.

-control_set_opt_threshold <arg> - (Optional) Threshold for synchronous control set optimization to decrease the number of control sets. Specifies how large the fanout of a control set should be before it starts using it as a control set. For example, if -control_set_opt_threshold is set to 10, a synchronous reset that only fans out to 5 registers would be moved to the D input logic, rather than using the reset line of a register. However, if -control_set_opt_threshold is set to 4, then the reset line is used. This option can be specified as "auto", or as an integer from 0 to 16. The default setting is "auto", and the actual threshold used under "auto" can vary depending on the selected device architecture.

-incremental - (Optional) Specify a DCP file for the incremental compilation flow. In the incremental synthesis flow, the netlist from the incremental DCP is applied to the design objects in the current design to reuse existing synthesis results when possible.

-max_bram <arg> - (Optional) Specify the maximum number of Block RAM to add to the design during synthesis. Specify a value >= 1, which should not exceed the available Block RAM count on the target device. If a value of -1 is used, the Vivado synthesis tool will not exceed the available Block RAM limit of the device. The default value is -1.
Note: A value of 0 directs Vivado synthesis to not infer Block RAMs in the design, but is not a recommended value.
-max_uram <arg> - (Optional) Specify the maximum number of Ultra RAM blocks (URAM) to add to the design during synthesis. Specify a value >= 1, which should not exceed the available URAM count on the target device. If a value of -1 is used, the Vivado synthesis tool will not exceed the available URAM block limit of the device. The default value is -1.
Note: A value of 0 directs Vivado synthesis to not infer URAM in the design, but is not a recommended value.
-max_dsp <arg> - (Optional) Specify the maximum number of DSPs to add to the design during synthesis. Specify a value >= 1, which should not exceed the available DSP count on the target device. If a value of -1 is used, the Vivado synthesis tool will not exceed the available limit of the device. The default value is -1.
Note: A value of 0 directs Vivado synthesis to not infer DSPs in the design, but is not a recommended value.

-max_bram_cascade_height <arg> - (Optional) Controls the maximum number of Block RAM that can be cascaded by the tool. A value of -1 lets Vivado synthesis choose up to the maximum number allowed for the target part. The default value is -1.

-max_uram_cascade_height <arg> - (Optional) Controls the maximum number of URAM that can be cascaded by the tool. A value of -1 lets Vivado synthesis choose up to the maximum number allowed for the target part. The default value is -1.

-retiming - (Optional) For non-Versal devices who do not have retiming turned On by default. Seeks to improve circuit performance for intra-clock sequential paths by automatically moving registers (register balancing) across combinatorial gates or LUTs. It maintains the original behavior and latency of the circuit and does not require changes to the RTL sources.
Note: If both -retiming and -no_retiming are set, retiming will not occur.
-no_retiming – (Optional). This is for Versal devices where retiming is On by default. Turns off the retiming feature.
Note: If both -retiming and -no_retiming are set, retiming will not occur.

-no_srlextract - (Optional) Prevents the extraction of shift registers so that they get implemented as simple registers.

-assert - (Optional) Enable VHDL assert statements to be evaluated. A severity level of failure stops the synthesis flow and produce an error.

-no_timing_driven - (Optional) Disables the default timing driven synthesis algorithm. This results in a reduced synthesis runtime, but ignores the effect of timing on synthesis.

-debug_log - (Optional) Prints an extended log file that is useful for debugging. Will have extra information about logic that was trimmed along with sections on the sizes of the RTL partitions and RTL Components. In addition, there will be more INFO/WARNING messages that are often ignored.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

The following example uses the set_property command to define the target part for the active project, then elaborates the source files and opens an RTL design: 
set_property part xc7vx485tffg1158-1 [current_project]
synth_design -rtl -name rtl_1
Note: The default source set, constraint set, and part will be used in this example.
The following example uses the find_top command to define the top of the current design for synthesis: 
synth_design -top [lindex [find_top] 0]
Note: Since find_top returns multiple possible candidates, choosing index 0 chooses the best top candidate for synthesis.
The following example runs synthesis on the current design, defining the top module and the target part, and specifying no flattening of the hierarchy. The results of the synthesis run are then opened in a netlist design: 
synth_design -top top -part xc7k70tfbg676-2 -flatten_hierarchy none
open_run synth_1 -name netlist_1

See Also