read_verilog - 2022.1 English

Description

Reads Verilog or SystemVerilog source files. This command is similar to the add_files command. The Verilog file is added to the source fileset as it is read. If the -library argument is specified, the file is added with the Library property defined appropriately.

You can use this command to read the contents of source files into the in-memory design, when running the Vivado® tool in Non Project mode, in which there is no project file to maintain and manage the various project source files. Refer to the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information on Non Project mode.

Because SystemVerilog is a superset of the Verilog language, the read_verilog command can read both file types. However, for SystemVerilog files, the -sv option needs to be specified for read_verilog to enable compilation in the SystemVerilog mode. In this mode, the tool recognizes and honors the SystemVerilog keywords and constructs.

You can have a mixture of both Verilog files (.v files), and SystemVerilog files (.sv files), as well as VHDL (using read_vhdl). When the tool compiles these files for synthesis, it creates separate "compilation units" for each file type. All files of the same type are compiled together.

Arguments

-library <arg> - (Optional) The library the Verilog file should reference. The default Verilog library is xil_defaultlib. The library name is ignored by Vivado synthesis.

Examples

read_verilog C:/Data/FPGA_Design/new_module.v

read_verilog -sv { file1.sv file2.sv file3.sv }
read_verilog { file1.v file2.v file3.v}

See Also

• add_files
• read_vhdl
• remove_files