The Vivado Design Suite contains a set
of methodology-related DRCs you can run using the report_methodology Tcl command. This command has rules for each of the
following design stages:
- Before synthesis in the elaborated RTL design to validate RTL constructs
- After synthesis to validate the netlist and constraints
- After implementation to validate constraints and timing related concerns.
Recommended: For maximum effect,
run the methodology DRCs at each design stage and address Critical Warnings and Warnings
prior to moving to the next stage.
Important:
Vivado IP integrator does not currently provide
methodology checks. Instead, you must use the
validate_bd_design command to identify connectivity and IP configuration
issues early on. Keep in mind that methodology violations identified later during
synthesis and implementation, such as non-recommended clock constraints or clock
topologies, might need to be addressed in the Vivado
IP integrator block design definition.For more information on the design methodology DRCs, see the report_methodology Tcl command in the Vivado Design Suite Tcl Command Reference Guide (UG835).