Clock Routing Tile Sharing Between Reconfigurable Partitions in DFX - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Versal devices allow clock tile splitting among multiple RPs. After you specify the range for the clock sources (e.g., MMCM and BUFG) to the Pblock, the DFX flow automatically uses the required clocking tiles for routing.

The following figure shows the RCLK row and the vertical NoC (VNoC) column sharing multiple RPs. In the RCLK row, two RPs share the same clock region; one above the RCLK row and one below. The VNoC tiles are also shared between multiple RPs.

Figure 1. RCLK Row and Vertical NoC Column Sharing Multiple RPs