Clock Phase Shift Modeling - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

A clock phase shift corresponds to a delayed clock waveform with respect to a reference clock due to special hardware in the clock path. In Xilinx devices, clock phase shift is usually introduced by the MMCM, XPLL, or DPLL primitives, when their output clock CLKOUT*_PHASE property is non-zero.

With analog deskew, the clock phase shift can be modeled either as a change in the clock waveform (PHASESHIFT_MODE=WAVEFORM) or as a delay through the MMCM or XPLL (PHASESHIFT_MODE=LATENCY). In Versal devices, the default modeling for the clock phase shift is as a delay through the clocking primitive. For more information about clock phase shift modeling and the PHASESHIFT_MODE property, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Following are additional notes:

  • For the DPLL or when an MMCM/XPLL is configured with digital deskew, the only supported configuration is PHASESHIFT_MODE=LATENCY.
  • If an MMCM/XPLL/DPLL is configured with digital deskew with the property PHASESHIFT_MODE=WAVEFORM, the following Warning is reported by Report Methodology:
    TIMING-54: The clock modifying block <MMCM/XPLL/DPLL> is configured for digital deskew and has PHASESHIFT_MODE=WAVEFORM. This combination is unsupported, and timing analysis will proceed by treating it as if PHASESHIFT_MODE=LATENCY. Change the specified cell configuration to PHASESHIFT_MODE=LATENCY and ensure that no timing constraints are written against the expectation of PHASESHIFT_MODE=WAVEFORM.