Parallel Clock Buffers - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Use parallel clock buffers to achieve the following:

  • Ensure predictable placement across implementation runs.

    When the parallel clock buffers are directly driven by the same input clock port, MMCM, XPLL, DPLL or GT*_QUAD, the buffers are always placed in the same clock region as their driver regardless of the netlist changes or logic placement variation.

  • Match the insertion delays between parallel branches of the clock tree.

    Xilinx recommends parallel buffers over cascaded clock buffers, especially when there are synchronous paths between the branches. When using cascaded buffers, the clock insertion delay is not matched between the branches of the clock trees even when using the CLOCK_DELAY_GROUP or USER_CLOCK_ROOT constraints. This can result in high clock skew, which makes timing closure challenging if not impossible.

Note: If possible, use the MBUFG* cells to minimize skew on synchronous CDC timing paths or when matching the insertion delay of multiple related clock networks. When using the MBUFG* cells, you should not use the CLOCK_DELAY_GROUP constraint.

The following figure shows three parallel global clock buffers driven by the MMCM CLKOUT0 port.

Figure 1. Parallel BUFGCE on MMCM Output