Specifying the RAM Activity for Jitter - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

The USER_RAM_AVERAGE_ACTIVITY constraint specifies a value that represents the average frequency of all UltraRAM and Block RAM on the device that can be switched (enabled/disabled). The value is used by the Vivado tools to model power supply noise induced by RAM switching and calculate jitter for global clocks in static timing analysis. The jitter is reported as a component of clock uncertainty in static timing analysis. If the USER_RAM_AVERAGE_ACTIVITY is not specified, the RAM_AVERAGE_ACTIVITY value computed by the Vivado tools is used for the jitter calculation and can increase the difficulty of timing closure.

Important: Xilinx recommends that you calculate the USER_RAM_AVERAGE_ACTIVITY for your design to reduce the difficulty of timing closure. For detailed information on RAM Activity Jitter and calculating the USER_RAM_AVERAGE_ACTIVITY for your design, see this link in the Versal ACAP Clocking Resources Architecture Manual (AM003).

The Vivado tool performs an estimate of RAM activity for flat designs based on the RAM device resources used, the RAM enable pins being connected to active signals, and the operating frequency of the RAMs. The Vivado tool assumes a pessimistic default value of 320 MHz for DFX designs. The RAM activity value computed by the Vivado tools is applied to the read-only RAM_AVERAGE_ACTIVITY property on the top-level [current_design] object. To reduce the pessimism in DFX designs, you can budget RAM Activity for your reconfigurable partitions and calculate the USER_RAM_AVERAGE_ACTIVITY for your design by using this link in the Versal ACAP Clocking Resources Architecture Manual (AM003).

To specify the USER_RAM_AVERAGE_ACTIVITY constraint, apply the constraint to the top-level [current_design] object in your XDC constraints:

set_property USER_RAM_AVERAGE_ACTIVITY 160 [current_design]

The following table shows how additional clock uncertainty caused by RAM switching can impact timing closure. In this example, a design has global clocks operating at 300 MHz, 400 MHz, and 500 MHz. The RAM_AVERAGE_ACTIVITY is 320, and the USER_RAM_AVERAGE_ACTIVITY constraint is calculated to be 160. Applying the constraint decreases the clock uncertainty for all paths in each clock domain, which makes achieving design timing closure less difficult.

Table 1. Pessimistic Default Clock Uncertainty vs. Specified RAM Activity Clock Uncertainty
Clock Domain RAM_AVERAGE_ACTIVITY 320 Clock Uncertainty USER_RAM_AVERAGE_ACTIVITY 160 Clock Uncertainty Clock Uncertainty Decrease
300 MHz 0.103 ns 0.073 ns -0.030 ns
400 MHz 0.089 ns 0.066 ns -0.023 ns
500 MHz 0.078 ns 0.058 ns -0.020 ns