Design Planning for Key IP Blocks - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Versal ACAP includes several essential hard IP. As part of carefully planning your design, you must analyze and configure these IP appropriately for your design.

The CIPS IP contains several key components for the Versal architecture, including the platform management controller (PMC), the processor subsystems (PS), and the Cache Coherent Interconnect for Accelerators (CCIX) PCIe® Module (CPM). The PMC manages programming and booting the Versal device, monitors the system, and protects the device from harmful attacks. Because the PMC is required to program and boot the device, the CIPS IP must be present in every Versal ACAP design. In addition, the CIPS IP can only be accessed from the Vivado® IP integrator. Therefore, all Versal ACAP designs include at least a portion of the design created using IP integrator, which contains the CIPS IP.
The NoC is a high-bandwidth, hardened interconnect that provides the backbone for all data movement in the Versal architecture. You interact with the NoC IP using standard AXI memory mapped or streaming interfaces. The NoC compiler aggregates the requested bandwidths and relative priorities for all traffic and allocates the physical routes appropriately. The NoC is the only way to access the Versal ACAP hardened memory controllers. In addition, NoC ports are available on the CIPS, throughout the AI Engine array and the programmable logic (PL) fabric.
In Versal devices, gigabit transceivers (GTs) are grouped into quads. This reduces overhead by enabling the GTs to share clocks and resets. As a result of this grouping, the GTs are separate from their parent IP, such as the MRMAC Ethernet IP. When a parent IP is placed on the IP integrator canvas, block automation handles connecting the parent IP to the GT quad. Pin planning for the GTs is incorporated into the Vivado Hard Block Planner and not part of the IP generation. For third-party IP, a bridge IP is available to facilitate the connections to the GT quad.