Converting Clock Gating to Clock Enable - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

If the code already contains clock gating constructs, or if it is intended for a different technology that requires such coding styles, Xilinx recommends that you use a synthesis tool that can remap gates placed within the clock path to clock enables in the data path. Doing so allows for a better mapping to the clocking resources; and simplifies the timing analysis of the circuit for data entering and exiting the gated domain. For example, use the -gated_clock_conversion auto option with Vivado synthesis to attempt automatic conversion to register clock enable logic. For the complex gated clock structures, use the GATED_CLOCK attribute in the RTL code to guide Vivado synthesis.