Kernel Interfaces - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2022-05-25
Version
2022.1 English

Xilinx strongly recommends creating PL kernels with the following interfaces:

  • At least one clock and one reset
  • Standard AXI interfaces:
    • Memory mapped AXI4 interface for memory mapped transfers over the NoC
    • AXI4-Stream for connections to other PL kernels, AI Engine graphs, or streaming platform ports
    • AXI4-Lite for control by the PS (software controllable kernels only)

For more information, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

Working with standard AXI interfaces enables design automation by the Vitis tools flow and reduces manual and error-prone tasks. However, it is also possible for PL kernels to have non-AXI interfaces. In this case, you need to manually and explicitly connect each of the non-AXI signals during the Vitis linking phase using the connectivity.connect option, as described in this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).