Control Signals and Control Sets - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

A control set is the grouping of control signals (set/reset, clock enable and clock) that drives any given SRL, LUTRAM, CLB, or IMUX register. For any unique combination of control signals, a unique control set is formed. This is important, because registers within a Versal ACAP slice share common control signals, which governs the packing of registers with different control sets into the same slice. For example, if a register with a given control set has just one register as a load, the other registers in the slice it occupies will be unusable for any registers with a different clock or set/reset signal. For more information, see this link in the Versal ACAP Configurable Logic Block Architecture Manual (AM005).

Designs with too many unique control sets might have many wasted resources as well as fewer options for placement, resulting in higher power and lower performance. Designs with fewer control sets have more options and flexibility in terms of placement, generally resulting in improved results.