Coding for FIFOs - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2022-05-25
Version
2022.1 English

The Versal architecture does not contain hardened FIFOs. Use one of the following methods when working with FIFOs in Versal devices:

RTL
Use XPM_FIFOs. The Vivado IDE Language Templates provide XPM_FIFO instantiations.
IP integrator
Instantiate the appropriate Xilinx FIFO IP.