Implementation Sub-Processes - 2021.2 English

Vivado Design Suite User Guide: Implementation (UG904)
Document ID
UG904
Release Date
2021-11-24
Version
2021.2 English

In project mode, the implementation commands are run in a fixed order. In non-project mode the commands can be run in a similar order, but can also be run repeatedly, iteratively, and in a different sequence than in project mode.

Important: Implementation Commands are re-entrant.

Implementation commands are re-entrant, which means that when an implementation command is called in non-project mode, it reads the design in memory, performs its tasks, and writes the resulting design back into memory. This provides more flexibility when running in non-project mode.

Examples:

  • opt_design followed by opt_design -remap

    The Remap operation occurs on the opt_design results.

  • place_design called on a design that contains some placed cells

    The existing cell placement is used as a starting point for place_design.

  • route_design called on a design that contains some routing

    The existing routing is used as a starting point for route_design.

  • route_design called on a design with unplaced cells

    Routing fails because cells must be placed first.

  • opt_design called on a fully-placed and routed design

    Logic optimization might optimize the logical netlist, creating new cells that are unplaced, and new nets that are unrouted. Placement and routing might need to be rerun to finish implementation.

Putting a design through the Vivado implementation process, whether in project mode or non-project mode, consists of several sub-processes:

Open Synthesized Design
Combines the netlist, the design constraints, and Xilinx target part data, to build the in-memory design to drive implementation.
Opt Design
Optimizes the logical design to make it easier to fit onto the target Xilinx device.
Power Opt Design (optional)
Optimizes design elements to reduce the power demands of the target Xilinx device.
Place Design
Places the design onto the target Xilinx device.
Post-Place Power Opt Design (optional)
Additional optimization to reduce power after placement.
Post-Place Phys Opt Design (optional)
Optimizes logic and placement using estimated timing based on placement. Includes replication of high fanout drivers.
Route Design
Routes the design onto the target Xilinx device.
Post-Route Phys Opt Design
Optimizes logic, placement, and routing using actual routed delays (optional).
Write Bitstream
Generates a bitstream for Xilinx device configuration (except Versal device).
Write Device Image
Generates a programmable device image for programming a Versal device.
Note: Although not technically part of an implementation run, Write Bitstream and Write Device Image are available as a separate step.

To provide a better understanding of the individual steps in the implementation process, the details of each step, and the associated Tcl commands, are documented in this chapter. The following table provides a list of sub-processes and their associated Tcl commands.

Table 1. Implementation Sub-processes and Associated Tcl Commands
Sub-Process Tcl Command
Open Synthesized Design synth_design
open_checkpoint
open_run
link_design
Opt Design opt_design
Power Opt Design power_opt_design
Place Design place_design
Phys Opt Design phys_opt_design
Route Design route_design
Write Bitstream (all devices except Versal) write_bitstream
Write Device Image (Versal devices) write_device_image

For a complete description of the Tcl reporting commands and their options, see the Vivado Design Suite Tcl Command Reference Guide (UG835).