Adding Constraints as Attribute Statements - 2021.2 English

Vivado Design Suite User Guide: Implementation (UG904)

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2021.2 English

Constraints can be added to HDL sources as attribute statements. Attributes can be added to both Verilog and VHDL sources to pass through to Vivado synthesis or Vivado implementation.

In some cases, constraints are available only as HDL attributes, and are not available in XDC. In those cases, the constraint must be specified as an attribute in the HDL source file. For example, Relatively Placed Macros (RPMs) must be defined using HDL attributes. An RPM is a set of logic elements (such as FF, LUT, DSP, and RAM) with relative placements.

You can define RPMs using U_SET and HU_SET attributes and define relative placements using Relative Location Attributes.

For more information about Relative Location Constraints, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).

For more information on constraints that are not supported in XDC, see the ISE to Vivado Design Suite Migration Guide (UG911).