Post-Placement Optimization - 2021.2 English

Vivado Design Suite User Guide: Implementation (UG904)

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2021.2 English

After all logic locations have been assigned, Post-Placement Optimization performs the final steps to improve timing and congestion. These include improving critical path placement and the optional BUFG insertion phase during which the placer can route high fanout nets on global routing tracks to free up fabric routing resources. High-fanout nets (fanout > 1000) driving control signals with a slack greater than 1.0 ns are considered for this optimization. The loads are split between critical loads and high positive slack loads. The high positive slack loads are driven through a BUFGCE which is placed at the nearest available site to the original driver, whereas the critical loads remain connected to the original driver. This optimization is performed only if there is no timing degradation. BUFG Insertion is on by default and can be disabled with the -no_bufg_opt option.