Saves the in-memory design into a design checkpoint file. The saved in-memory design includes the following:
- Logical netlist
- Physical and timing related constraints
- Xilinx part data
- Placement and routing information
In Non-Project Mode, the design checkpoint file saves the design and allows it to be reloaded for further analysis and modification.
For more information, see Using Checkpoints to Save and Restore Design Snapshots.