VHDL Coding Example With Unexpected Results - 2021.2 English

clk_b <= clk;
clk_prcs : process (clk)
begin
  if (clk'event and clk='1') then
    result <= data;
  end if;
end process;
clk_b_prcs : process (clk_b)
begin
  if (clk_b'event and clk_b='1') then
    result1 <= result;
  end if;
end process;

In this example, there are two synchronous processes:

• clk_prcs
• clk_b_prcs

The simulator performs the clk_b <= clk assignment before advancing the simulation time. As a result, events that should occur in two clock edges occur in one clock edge instead, causing a race condition.

Recommended ways to introduce causality in simulators for such cases include:

• Do not change clock and data at the same time. Insert a delay at every output.
• Use the same clock.
• Force a delta delay by using a temporary signal, as shown in the following example:

  clk_b <= clk;
  clk_prcs : process (clk)
  begin 
    if (clk'event and clk='1') then
      result <= data;
    end if;
  end process;
  result_temp <= result;
  clk_b_prcs : process (clk_b)
  begin
  if (clk_b'event and clk_b='1') then
      result1 <= result_temp;
    end if;
  end process;

Most event-based simulators can display delta cycles. Use this to your advantage when debugging simulation issues.