Running Post-Synthesis and Post-Implementation Simulations - 2021.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2021-10-22
Version
2021.2 English

At post-synthesis and post-implementation, you can run a functional or a Verilog timing simulation. The following figure illustrates the post-synthesis and post-implementation simulation process:

Figure 1. Post-Synthesis and Post-Implementation Simulation
Run Synthesis or Implementation Parse Using xvlog/xvhdl Simulation Usingxsim <snapshot> Create Netlistwrite_verilog or write_vhdl Post-SynthesisPost-ImplementationSimulation Gather Files(Create Project File ) Compile and ElaborateUsing xelab Debug in WaveformOr Self-checking Test Bench X12985 For Timing Simulationwrite_sdf

The following is an example of running a post-synthesis functional simulation from the command line:

synth_design -top top -part xc7k70tfbg676-2
open_run synth_1 -name netlist_1
write_verilog -mode funcsim test_synth.v
launch_simulation
Tip: When you run a post-synthesis or post-implementation timing simulation, you must run the write_sdf command after the write_verilog command, and the appropriate annotate command is needed for elaboration and simulation.