Running Timing Simulation Using Third-Party Tools - 2021.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2021-10-22
Version
2021.2 English
Tip: Post-Synthesis timing simulation uses the estimated timing delay from the synthesized netlist. Post-Implementation timing simulation uses actual timing delays.

When you run Post-Synthesis and Post-Implementation timing simulation, the simulators include:

  • Gate-level netlist containing SIMPRIMS library components
  • SECUREIP
  • Standard Delay Format (SDF) files

You define the overall design functionality in the beginning. When the design is implemented, accurate timing information is available.

To create the netlist and SDF, the Vivado Design Suite:

  • Calls the netlist writer, write_verilog with the -mode timesim switch and write_sdf (SDF annotator)
  • Sends the generated netlist to the target simulator

You control these options using Simulation Settings as described in Using Simulation Settings.

Important: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only. There is no support for VHDL timing simulation. If you are a VHDL user, you can run post-synthesis and post-implementation functional simulation (in which case no SDF annotation is required and the simulation netlist uses the UNISIM library). You can create the netlist using the write_vhdl Tcl command. For usage information, refer to the Vivado Design Suite Tcl Command Reference Guide (UG835).

Post-Synthesis Timing Simulation

When synthesis runs successfully, the Run Simulation > Post-Synthesis Timing Simulation option becomes available.

After you select a post-synthesis timing simulation, the timing netlist and the SDF file are generated. The netlist files includes $sdf_annotate command so that the generated SDF file is picked up.

Post-Implementation Timing Simulations

When post-implementation is successful, the Run Simulation > Post-Implementation Timing Simulation option becomes available.

After you select a post-implementation timing simulation, the timing netlist and the SDF file are generated. The netlist files includes $sdf_annotate command so that the generated SDF file is picked up.

Annotating the SDF File for Timing Simulation

When you specified simulation settings, you specified whether or not to create an SDF file and whether the process corner would be set to fast or slow.

Tip: To find the SDF file options settings, in the Vivado IDE Flow Navigator, right-click Simulation and select Simulation Settings. In the Settings dialog box, select Simulation category and click Netlist tab.

Based on the specified process corner, the SDF file contains different min and max numbers.

Recommended: To run a setup check, create an SDF file with -process_corner slow, and use the max column from the SDF file.

To run a hold check, create an SDF file with the -process_corner fast, and use the min column from the SDF file. The method for specifying which SDF delay field to use is dependent on the simulation tool you are using. Refer to the specific simulation tool documentation for information on how to set this option.

To get full coverage run all four timing simulations, specify as follows:

  1. Slow corner: SDFMIN and SDFMAX
  2. Fast corner: SDFMIN and SDFMAX

Running Standalone Timing Simulation

If you are running timing simulation from Vivado IDE, it will add the timing simulation related switches to simulator. If you run standalone timing simulation, make sure to pass the following switch to simulators during elaboration:

For VCS:

+pulse_e/<number> and +pulse_r/<number>  +transport_int_delays

During elaboration (with VCS)

For ModelSim/Questa Advanced Simulator:

+transport_int_delays +pulse_int_e/0 +pulse_int_r/0

During elaboration (with vsim)

Important: The Vivado simulator models use interconnect delays; consequently, additional switches are required for proper timing simulation, as follows: -transport_int_delays -pulse_r 0 -pulse_int_r 0. Table 1 provides descriptions for the these commands.