| Verilog options |
Browse to set Verilog include path and to define macro |
| Generics/Parameters options |
Specify or browse to set the generic/parameter value |
| questasim.compile.tcl.pre |
TCL file containing set of commands that should be invoked before launch of compilation |
| questasim.compile.vhdl_syntax |
Specify VHDL syntax |
| questasim.compile.use_explicit_decl |
Log all signals |
| questasim.compile.load_glbl |
Load GLBL module |
| questasim.compile.vlog.more_options |
More VLOG compilation options |
| questasim.compile.vcom.more_options |
More VCOM compilation options |
| questasim.compile.sccom.cores |
Specify the number of process cores to run in parallel |
| questasim.compile.sccom.more_options |
More SCCOM compilation options |