A test bench is Hardware Description Language (HDL) code written for the simulator that:
- Instantiates and initializes the design.
- Generates and applies stimulus to the design.
- Monitors the design output result and checks for functional correctness (optional).
You can also set up the test bench to display the simulation output to a file, a waveform, or to a display screen. A test bench can be simple in structure and can sequentially apply stimulus to specific inputs.
A test bench can also be complex, and can include:
- Subroutine calls
- Stimulus that is read in from external files
- Conditional stimulus
- Other more complex structures
The advantages of a test bench over interactive simulation are that it:
- Allows repeatable simulation throughout the design process
- Provides documentation of the test conditions
The following bullets are recommendations for creating an effective test bench.
- Always specify the
`timescalein Verilog test bench files. For example:`timescale 1ns/1ps - Initialize all inputs to the design within the test bench at simulation time zero to properly begin simulation with known values.
- Apply stimulus data after 100 ns to account for the default Global Set/Reset (GSR) pulse used in functional and timing-based simulation.
- Begin the clock source before the Global Set/Reset (GSR) is released.
For more information about test benches, see Writing Efficient Test Benches (XAPP199).
Tip: When you create a test bench, remember that the GSR pulse occurs automatically in the post-synthesis and post-implementation timing simulation. This holds all registers in reset for the first 100 ns of the simulation.