create_sysgen - 2021.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2021.2 English

Create DSP source for Xilinx System Generator and add to the source fileset


create_sysgen [‑quiet] [‑verbose] <name>


Name for the new sub module.


Name Description
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<name> Sub module name




Create a DSP sub-module for use in the current project, and add it to the source files.

This command will launch System Generator for DSP to let you design the hardware portion of your system design. System Generator is a DSP design tool from Xilinx that allows the RTL source files, Simulink® and MATLAB® software models, and C/C++ components of a DSP system to come together in a single simulation and implementation environment.

For more information on using specific features of the tool refer to System Generator for DSP Getting Started Guide (UG639).

You can also add existing DSP model files (.mdl) from System Generator into the current project using the add_files command.

The command returns the name of the DSP module created and added to the project.


-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<name> - (Required) The name of the DSP module to create and add to the current project.


The following example launches System Generator and allows you to define and configure the specified DSP module:
create_sysgen DSP_mod1