Training Resources
Xilinx provides a variety
of training courses and QuickTake videos to help you learn more about
the concepts presented in this document. Use these links to explore
related training resources:
- UltraFast Design Methodology Training Course
- Designing with UltraScale and UltraScale+ Architectures Training Course
- Designing FPGAs Using the Vivado Design Suite Training Course
- Vivado Design Suite QuickTake Video: Using the Non-Project Batch Flow
- Vivado Design Suite QuickTake Video: Using Tcl Scripts as Constraint Files in Vivado
References
Tcl Developer Xchange
Tcl reference material is available on the Internet. Xilinx recommends the Tcl Developer Xchange, which maintains the open source code base for Tcl, and is located at:
An introductory tutorial is available at:
About SDC
Synopsys Design Constraints (SDC) is an accepted industry standard for communicating design intent to tools, particularly for timing analysis. A reference copy of the SDC specification is available from Synopsys by registering for the TAP-in program at:
http://www.synopsys.com/Community/Interoperability/Pages/TapinSDC.aspx