You can use Xilinx simulation libraries with any simulator that supports the VHDL-93 and Verilog-2001 language standards. Certain delay and modeling information is built into the libraries; this is required to simulate the Xilinx hardware devices correctly.
Use non-blocking assignments for blocks within clocking edges. Otherwise, write code using blocking assignments in Verilog. Similarly, use variable assignments for local computations within a process, and use signal assignments when you want data-flow across processes.
If the data changes at the same time as a clock, it is possible that the simulator will schedule the data input to occur after the clock edge. The data does not go through until the next clock edge, although it is possible that the intent was to have the data clocked in before the first clock edge.
When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. The Xilinx libraries are divided into categories based on the function of the model.
The following table lists the Xilinx-provided simulation libraries:
| Library Name | Description | VHDL Library Name | Verilog Library Name |
|---|---|---|---|
| UNISIM | Functional simulation of Xilinx primitives. | UNISIM | UNISIMS_VER |
| UNIMACRO | Functional simulation of Xilinx macros. | UNIMACRO | UNIMACRO_VER |
| UNIFAST | Fast simulation library. | UNIFAST | UNIFAST_VER |
| SIMPRIM | Timing simulation of Xilinx primitives. | N/A | SIMPRIMS_VER 1 |
| SECUREIP |
Simulation library for both functional and timing simulation of Xilinx device features, such as the PCIe IP, Gigabit Transceiver etc., You can find the list of IP's under SECUREIP at the following location: <Vivado_Install_Dir>/data/secureip |
SECUREIP | SECUREIP |
| XPM | Functional simulation of Xilinx primitives | XPM | XPM 2 |
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The following table lists the required simulation libraries at each simulation point.
| Simulation Point | UNISIM | UNIFAST | UNIMACRO | SECUREIP | SIMPRIM (Verilog Only) | SDF |
|---|---|---|---|---|---|---|
| 1. Register Transfer Level (RTL) (Behavioral) | Yes | Yes | Yes | Yes | N/A | No |
| 2. Post-Synthesis Simulation (Functional) | Yes | Yes | N/A | Yes | N/A | N/A |
| 3. Post-Synthesis Simulation (Timing) | N/A | N/A | N/A | Yes | Yes | Yes |
| 4. Post-Implementation Simulation (Functional) | Yes | Yes | N/A | Yes | N/A | N/A |
| 5. Post-Implementation Simulation (Timing) | N/A | N/A | N/A | Yes | Yes | Yes |
The following table lists the library locations.
| Library | HDL Type | Location |
|---|---|---|
| UNISIM | Verilog | <Vivado_Install_Dir>/data/verilog/src/unisims |
| VHDL | <Vivado_Install_Dir>/data/vhdl/src/unisims | |
| UNIFAST | Verilog | <Vivado_Install_Dir>/data/verilog/src/unifast |
| VHDL | <Vivado_Install_Dir>/data/vhdl/src/unifast | |
| UNIMACRO | Verilog | <Vivado_Install_Dir>/data/verilog/src/unimacro |
| VHDL | <Vivado_Install_Dir>/data/vhdl/src/unimacro | |
| SECUREIP | Verilog | <Vivado_Install_Dir>/data/secureip/ |
The following subsections describe the libraries in more detail.