Key Steps in a Mixed Language Simulation - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2021-06-16
Version
2021.1 English
  1. Optionally, specify the search order for VHDL components or Verilog/SV modules in the design libraries of a mixed language project.
  2. Use xelab -L to specify the binding order of a VHDL component or a Verilog/SV module in the design libraries of a mixed language project.
    Note: The library search order specified by -L is used for binding Verilog modules to other Verilog modules as well.