Compiling Simulation Libraries Using Vivado IDE

Compiling Simulation Libraries Using Vivado IDE - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2021-06-16

Version

2021.1 English

Select Tools > Compile Simulation Libraries to open the dialog box shown in the following figure.

Figure 1. Compile Simulation Libraries Dialog Box

Set the following options:

Language: Compiles libraries for the specified language. If this option is not specified, then the language is set to correspond with the selected simulator (above). For multi-language simulators, both Verilog and VHDL libraries are compiled.

Library: Specifies the simulation library to compile. By default, the compile_simlib command compiles all simulation libraries.

Family: Compiles selected libraries to the specified device family. All device families are generated by default.

Compiled library location: Specifies the directory path for saving the compiled library results. By default, the libraries are saved in the current working directory in Non-Project mode, and the libraries are saved in the <project>/<project>.cache/compile_simlib directory in Project mode. See the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information on Project and Non-Project modes.
Tip: Because the Vivado simulator has pre-compiled libraries, it is not necessary to identify the library location.

Simulator executable path: Specifies the directory to locate the simulator executable. This option is required if the target simulator is not specified in the $PATH or %PATH% environment variable, or to override the path from the $PATH or %PATH% environment variable.
GCC executable path: Specifies the directory to locate GCC installation. This option is required if GCC path settings are not done as mentioned in GCC Path Settings. Ignore if you are not using SystemC IP.

Miscellaneous Options: Specify additional options for the compile_simlib Tcl command.

Compile Xilinx IP: Enable or disable compiling simulation libraries for Xilinx IP.

Overwrite current pre-compiled libraries: Overwrites the current pre-compiled libraries.

Compile 32-bit libraries: Performs simulator compilation in 32-bit mode instead of the default 64-bit compilation.

Verbose: Temporarily overrides any message limits and return all messages from this command.

Command: Shows the Tcl command equivalent for the options you enter in the dialog box.
Tip: You can use the value of the Command field to generate a simulation library in Tcl/non-project mode.