Xilinx® block RAM memory is a true dual-port RAM where both ports can access any memory location at any time. Be sure that the same address space is not accessed for reading and writing at the same time. This causes a block RAM address collision. These are valid collisions, because the data that is being read from the read port is not valid.
In the hardware, the value that is read might be the old data, the new data, or a combination of the old data and the new data.
In simulation, this is modeled by outputting X because the value read is unknown. For more information on block RAM collisions, see the user guide for the device.
In certain applications, this situation cannot be avoided or designed around. In these cases, the block RAM can be configured not to look for these violations. This is controlled by the generic (VHDL) or parameter (Verilog) SIM_COLLISION_CHECK string in block RAM primitives.
The following table shows the string options you can use with SIM_COLLISION_CHECK to control simulation behavior in the event of a collision.
| String | Write Collision Messages | Write Xs on the Output |
|---|---|---|
| ALL | Yes | Yes |
| WARNING_ONLY | Yes | No. Applies only at the time of collision. Subsequent reads of the same address space could produce Xs on the output. |
| GENERATE_X_ONLY | No | Yes |
| None | No | No. Applies only at the time of collision. Subsequent reads of the same address space could produce Xs on the output. |
Apply the SIM_COLLISION_CHECK at an instance level so you can change the setting for each block RAM instance.