Objects Window - 2021.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2021-06-16

Version

2021.1 English

The Objects window displays the HDL simulation objects associated with the scope selected in the Scope window, as shown in the following figure.

Figure 1. Objects Window

Icons beside the HDL objects show the type or port mode of each object. This view lists the Name, Value, and Data Type of the simulation objects.

You can obtain the current value of an object by typing the following in the Tcl Console.

get_value <hdl_object>

Tip: To limit the number of digits to display for vectors, use the

set_property array_display_limit
                <bits> [current_sim]

command, where <bits> is the number of bits to display.

The following are the options available at the top of the Objects window. Click Settings to view the selected objects in the Objects window. Use this to filter or limit the contents of the Objects window.

Search: You can use the Search option to search for an object name.
Settings: Settings option allows you to display or hide various HDL objects in the Objects window.

Objects Context Menu

When you right-click an object in the Objects window, a context menu (shown in Objects Window) appears. The options in the context menu are described below.

Figure 2. Context Menu in Objects Window

Add to Wave Window: Add the selected object to the waveform configuration. Alternately, you can drag and drop the objects from the Objects window to the Name column of the wave window.
Log to Wave Database: Logs events of the selected object to the waveform database (WDB) for later viewing in the wave window.
Tip: By default, the Vivado simulator suppresses the logging of large HDL objects. To change the size limit of logged objects, use the set_property trace_limit <size> [current_sim] Tcl command, where <size> is the number of scalar elements in the HDL object.
Show in Wave Window: Highlights the selected object in the wave window.
Default Radix: Set the default radix for all objects in the Objects window and text editor. The default radix is Hexadecimal. You can change this option from the context menu.
Tcl command:
```
set_property radix <new radix> [current_sim]
```
Where <new radix> is any of the following:
- bin
- unsigned (for unsigned decimal)
- hex
- dec (for signed decimal)
- ascii
- oct
- smag (for signed magnitude)
Note: If you need to change the radix of an individual signal, use radix option from the context menu.
Radix: Select the numerical format to use when displaying the value of the selected object in the Objects window and in the source code window.
You can change the radix of an individual object as follows:
1. Right-click an object in the Objects window.
2. From the context menu, select Radix and the format you want to use:
  - Default
  - Binary
  - Hexadecimal
  - Octal
  - ASCII
  - Unsigned Decimal
  - Signed Decimal
  - Signed Magnitude
Tip: If you change the radix in the Objects window, it will not be reflected in the wave window.
Show as Enumeration: Select to display the values of a SystemVerilog enumeration signal or variable using enumeration labels.
Note: This menu item is enabled only for SystemVerilog enumerations. If unchecked, all values of the enumeration object display numerically according to the radix set for the object. If checked, those values for which the enumeration declaration defines a label display the label text, and all other values display numerically.
Report Drivers: Display in the Tcl Console a report of the HDL processes that assign values to the selected object.
Go To Source Code: Open the source code at the definition of the selected object.
Force Constant: Forces the selected object to a constant value.
Force Clock: Forces the selected object to an oscillating value.
Remove Force: Removes any force on the selected object.
Tip: If you notice that some HDL objects do not appear in the Waveform Viewer, it is because Vivado simulator does not support waveform tracing of some HDL objects, such as named events in Verilog and local variables.