- Open the Vivado IDE:
- Click
In this lab you will use the same design as Lab 5: Using AXI Interfaces and IP Integrator, but this time you will create the design using a Tcl file, rather than the interactive process.
.
- Click
- Using the Tcl console as shown in the following figure:
- Type
cd C:\ug1498-model-composer-sys-gen-tutorial\HDL_Library\Lab6\IPI_Project
to change to the project directory. - Type
source lab6_design.tcl
to create the RTL design.
This creates the project, creates the IP integrator design and builds the implementation (RTL synthesis, followed by place and route). This may take some time to complete (same as the final step of Lab 5: Using AXI Interfaces and IP Integrator).
When it completes:
- Type
- Click Open Implemented Design in the Flow Navigator pane.
- From the Vivado IDE main menu select .
- Click Next in the Export Hardware Platform page.
- Select the Include Bitstream option
in the Output page and
click Next.
- Leave the XSA file name and the
Export to fields at the default
setting and click Next.
- Click Finish to export the hardware.
- Open the Vitis IDE:
- Click .
- Select the workspace space directory to store preferences and click
Launch.
- From the Vitis IDE, select Create Application Project.
- Click Next in the Welcome page.
- Switch to the Create a new platform from hardware(XSA) tab and click Browse to create a custom platform from the XSA.
- Navigate to design_1_wrapper.xsa and click Open.
, select - Enter the application project name
Des_Test
in the Application project name field. - In the Target processor section,
select the processor ps7_cortexa9_0 and
click Next.
- Click Next.
- In the Domain page ensure the CPU selected is ps7_cortexa9_0 and click Next.
- Select the Hello World template and click Finish.
- Expand the design_1_wrapper container as shown to confirm the AXI4-Lite driver code is included in the
project.
- Power up the ZC702 board to program the FPGA.
- Click Program.
The Done LED (DS3) goes ON, on the FPGA board.
and from the resulting window, click - Click Show
view window, type
Vitis
, select Vitis Serial Terminal and click Open.
and in the - To set up the terminal in the Vitis
Serial Terminal view, click the + icon and perform the following:
- Select the COM port to which the USB UART cable is connected. On Windows, if you are unsure, open the Device Manager and identify the port with the "Silicon Labs" driver under Ports (COM & LPT).
- Change the Baud Rate to
115200
. - Click OK to exit the Terminal Settings dialog box.
- Check that the terminal is connected by the message in tab title bar.
- Right-click the application project Des_Test in the Explorer view, select Build Project.
When this completes, you will see the message “Build Finished” in the console.
- Right-click on application project Des_Test, select .
- Switch to the Vitis Serial
Terminal tab and confirm that
Hello World
was received. - Expand the container
Des_Test
and then expand the containersrc
. - Double-click the helloworld.c file.
- Replace the contents of this file with the contents of the file hello_world_final.c from the lab6 directory.
- Save the helloworld.c source code.
- Right-click application project Des_Test in the Explorer view, and select Build Project.
When this completes, you will see the message “Build Finished” in the console.
- Right-click again and select Note: If a window opens displaying the text “Run Session is already active”, click OK in that window.
.
- Review the results in the Vitis Serial
Terminal tab (shown in the following figure).