Step 2: Developing Software and Running it on the Zynq-7000 System - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)
Document ID
UG1498
Release Date
2021-07-16
Version
2021.1 English
  1. Open the Vivado IDE:
    • Click Windows > Xilinx Design Tools > Vitis 2021.1.

      In this lab you will use the same design as Lab 5: Using AXI Interfaces and IP Integrator, but this time you will create the design using a Tcl file, rather than the interactive process.

  2. Using the Tcl console as shown in the following figure:
    1. Type cd C:\ug1498-model-composer-sys-gen-tutorial\HDL_Library\Lab6\IPI_Project to change to the project directory.
    2. Type source lab6_design.tcl to create the RTL design.

      This creates the project, creates the IP integrator design and builds the implementation (RTL synthesis, followed by place and route). This may take some time to complete (same as the final step of Lab 5: Using AXI Interfaces and IP Integrator).

      When it completes:

  3. Click Open Implemented Design in the Flow Navigator pane.
  4. From the Vivado IDE main menu select File > Export > Export Hardware.
  5. Click Next in the Export Hardware Platform page.

  6. Select the Include Bitstream option in the Output page and click Next.

  7. Leave the XSA file name and the Export to fields at the default setting and click Next.

  8. Click Finish to export the hardware.
  9. Open the Vitis IDE:
    • Click Windows > Xilinx Design Tools > Vitis 2021.1.
  10. Select the workspace space directory to store preferences and click Launch.

  11. From the Vitis IDE, select Create Application Project.
  12. Click Next in the Welcome page.
  13. Switch to the Create a new platform from hardware(XSA) tab and click Browse to create a custom platform from the XSA.
  14. Navigate to Lab6 > IPI_Project > project_1, select design_1_wrapper.xsa and click Open.

  15. Enter the application project name Des_Test in the Application project name field.
  16. In the Target processor section, select the processor ps7_cortexa9_0 and click Next.

  17. Click Next.
  18. In the Domain page ensure the CPU selected is ps7_cortexa9_0 and click Next.
  19. Select the Hello World template and click Finish.
  20. Expand the design_1_wrapper container as shown to confirm the AXI4-Lite driver code is included in the project.

  21. Power up the ZC702 board to program the FPGA.
  22. Click Xilinx > Program Device and from the resulting window, click Program.

    The Done LED (DS3) goes ON, on the FPGA board.

  23. Click Window > Show View and in the Show view window, type Vitis, select Vitis Serial Terminal and click Open.

  24. To set up the terminal in the Vitis Serial Terminal view, click the + icon and perform the following:

    1. Select the COM port to which the USB UART cable is connected. On Windows, if you are unsure, open the Device Manager and identify the port with the "Silicon Labs" driver under Ports (COM & LPT).
    2. Change the Baud Rate to 115200.
    3. Click OK to exit the Terminal Settings dialog box.
    4. Check that the terminal is connected by the message in tab title bar.
  25. Right-click the application project Des_Test in the Explorer view, select Build Project.

    When this completes, you will see the message “Build Finished” in the console.

  26. Right-click on application project Des_Test, select Run As > Launch on Hardware.
  27. Switch to the Vitis Serial Terminal tab and confirm that Hello World was received.
  28. Expand the container Des_Test and then expand the container src.
  29. Double-click the helloworld.c file.
  30. Replace the contents of this file with the contents of the file hello_world_final.c from the lab6 directory.
  31. Save the helloworld.c source code.
  32. Right-click application project Des_Test in the Explorer view, and select Build Project.

    When this completes, you will see the message “Build Finished” in the console.

  33. Right-click again and select Run As > Launch on Hardware.
    Note: If a window opens displaying the text “Run Session is already active”, click OK in that window.
  34. Review the results in the Vitis Serial Terminal tab (shown in the following figure).