Step 2: Mapping Interfaces - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)

Document ID
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2021.1 English
  1. Double-click the CodeGen_Interface.slx model in your Current Folder to open the design for this lab section.

    This is a slightly modified version of the Edge Detection algorithm that uses the YCbCr video format at the input and output.

  2. Simulate the model to see the results in the Video Viewer blocks. Stop simulation before continuing to the next step.
  3. Open the Simulink Library browser, navigate to the Xilinx Toolbox > HLS > Tools sub-library and add the Interface Spec block inside the Edge Detection subsystem as shown in the following figure.

  4. Double-click the Interface Spec block to open the block interface.

    The Interface Spec block allows you to control what RTL interfaces should be synthesized for the ports of the subsystem in which the block is instantiated. This affects only code generation; it has no effect on Simulink simulation of your design.

    The information gathered by the Interface Spec block consists of three parts (represented as three Tabs on the block).

    Function Protocol
    This is the block-level Interface Protocol which tells the IP when to start processing data. It is also used by the IP to indicate whether it accepts new data, or whether it has completed an operation, or whether it is idle.
    Input Ports
    Detects the Input ports in your subsystem automatically and allows specifying the port-level Interface Protocol for each input port of the subsystem.
    Output Ports
    Similar to the Input Ports tab, this tab detects the Output ports in the subsystem, and allows specifying the port-level Interface Protocol for each output port of the subsystem.
  5. For this design, leave the Function Protocol mode at the default AXI4-Lite Slave and configure the Input ports and Output ports tabs as shown in the following figures.

    • The Bundle parameter is used in conjunction with the AXI4-Lite or AXI4-Stream (video) interfaces to indicate that multiple ports should be grouped into the same interface. It lets you bundle multiple input/output signals with the same specified bundle name into a single interface port and assigns the corresponding name to the RTL port.

      For example in this case, the specified settings on the Input ports tab result in the YCbCr inputs being mapped to AXI4-Stream (video) interfaces and bundled together as an image_in port in the generated IP while the YCbCr outputs are bundled together as an image_out port.

    • The Video Format drop-down menu lets you select between the following formats:
      • YUV 4:2:2
      • YUV 4:4:4
      • RGB
      • Mono/Sensor
    • The Video Component drop-down menu is used to subsequently select the right component: R, G, B, Y, U, V.