Step 1: Creating Clock Domain Hierarchies - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)
Document ID
UG1498
Release Date
2021-07-16
Version
2021.1 English
In this step you will review a design in which different parts of the design operate at different data rates and partition the design into subsystems to be implemented in different clock domains.
  1. Invoke Model Composer:
    • On Windows systems select Windows > Xilinx Design Tools > Vitis Model Composer 2021.1.
    • On Linux systems, type model_composer at the command prompt.
  2. Navigate to the Lab4 folder: \HDL_Library\Lab4.
  3. At the command prompt, type open Lab4_1.slx.

    This opens the Simulink design shown in the following figure. This design is composed of three basic parts:

    • The channel filter digitally converts the incoming signal (491.52 MSPS) to near baseband (61.44 MSPS) using a classic multi-rate filter: the use of two half-band filters followed by a decimation of 2 stage filter, which requires significantly fewer coefficients than a single large filter.
    • The output section gain-controls the output for subsequent blocks which will use the data.
    • The gain is controlled from the POWER_SCALE input.


  4. Click the Run simulation button to simulate the design.

    In the following figure Sample Time Display is enabled with colors (right-click in the canvas, Sample Time Display > Colors), and shows clearly that the design is running at multiple data rates.



  5. The Model Composer environment automatically propagates the different data rates through the design.

    When a multi-rate design such as this is implemented in hardware, the most optimal implementation is to use a clock at the same frequency as the data; however, the clock is abstracted away in this environment. The following methodology demonstrates how to create this ideal implementation in the most efficient manner.

  6. To efficiently implement a multi-rate (or multi-clock) design using Model Composer you should capture each part running at the same data rate (or clock frequency) in its own hierarchy with its own System Generator token. The separate hierarchies should then be linked with FIFOs.
  7. The current design has two obvious, and one less obvious, clock domains:
    • The gain control input POWER_SCALE could be configurable from a CPU and therefore can run at the same clock frequency as the CPU.
    • The actual gain-control logic on the output stage should run at the same frequency as the output data from the FIR. This will allow it to more efficiently connect to subsequent blocks in the system.
    • The less obvious region is the filter-chain. Remember from Lab 1 that complex IP provided with Model Composer, such as the FIR Compiler, automatically takes advantage of over-sampling to provide the most efficient hardware. For example, rather than use 40 multipliers running at 100 MHz, the FIR Compiler will use only eight multipliers if clocked at 500 MHz (= 40*100/500). The entire filter chain can therefore be grouped into a single clock domain. The first FIR Compiler instance will execute at the maximum clock rate and subsequent instances will automatically take advantage of over-sampling.

    You will start by grouping these regions into different hierarchies.

  8. Select all the blocks in the filter chain – all those to be in the same clock domain, including the FDATool instances - as shown in the following figure.
  9. Select Create Subsystem, also as shown in the following figure, to create a new subsystem.

  10. Select the instance name subsystem and change this to DDC to obtain the design shown.

  11. Select the components in the output path and create a subsystem named Gain Control.

  12. Finally, select the Gateway In instance POWER_SCALE and Constant to create a new subsystem called CTRL. The final grouped design is shown in the following figure.

When this design is complete, the logic within each subsystem will execute at different clock frequencies. The clock domains might not be synchronous with each other. There is presently nothing to prevent incorrect data being sampled between one subsystem and another subsystem.

In the next step you will create asynchronous channels between the different domains to ensure data will asynchronously and safely cross between the different clock domains when the design is implemented in hardware.