Lab 3: Timing and Resource Analysis - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)

Document ID
Release Date
2021.1 English

In this lab, you learn how to verify the functionality of your designs by simulating in Simulink® to ensure that your Model Composer design is correct when you implement the design in your target Xilinx® device.


After completing this lab, you will be able to:

  • Identify timing issues in the HDL files generated by Model Composer and discover the source of the timing violations in your design.
  • Perform resource analysis and access the existing resource analysis results, along with recommendations to optimize.


This lab has two primary parts:

  • In Step 1 you will learn how to do timing analysis in Model Composer.
  • In Step 2 you will learn how to perform resource analysis in Model Composer.