Step 1: Review the AXI4-Lite Interface Drivers - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)
Document ID
UG1498
Release Date
2021-07-16
Version
2021.1 English
In this step you review how AXI4-Lite interface drivers are provided when a design with an AXI4-Lite interface is saved.

This exercise uses the same design as Lab 5: Using AXI Interfaces and IP Integrator.

  1. Invoke Vitis Model Composer and use the Current Folder browser to change the directory to: \HDL_Library\Lab6.
  2. At the command prompt, type open Lab6_1.slx. This opens the design as shown in the following figure.

    This design uses a number of AXI interfaces. These interfaces were reviewed in Lab 5: Using AXI Interfaces and IP Integrator and the review is repeated here with additional details on the AXI4-Lite register addressing.

    • Using AXI interfaces allows a design exported to the Vivado IP Catalog to be efficiently integrated into a larger system using IP integrator.
    • It is not a requirement for designs exported to the IP Catalog to use AXI interfaces. The design uses the following AXI interfaces:
      • An AXI4-Stream interface is used for ports s_axis_source_*. All Gateway In and Out signals are prefixed with same name (s_axis_source_) ensuring they are grouped into the same interface. The suffix for all ports are valid AXI4-Stream interface signal names (tvalid, tlast, and tdata).
      • An AXI4-Lite interface is used for the remaining ports. You can confirm this by performing the following steps:
  3. Double-click Gateway In decrypt (or any of reset, Keys[63:32], Keys[31:0], parity_err).
  4. In the Properties Editor select the Implementation tab.
  5. Confirm the Interface is specified as AXI4-Lite in the Interface options.

    Also note how the address of this port may be automatically assigned (as the current setting of Auto assign address offset indicates), or the address may be manually specified.

  6. Click OK to exit the Properties Editor.

    Details on simulating the design are provided in the canvas notes. For this exercise, you will concentrate on exporting the design to the Vivado IP catalog and use the IP in an existing design.

  7. In the System Generator token, select Generate to generate a design in IP Catalog format.
  8. Click OK to dismiss the Compilation status dialog box.
  9. Click OK to dismiss the System Generator token.
  10. In the file system, navigate to the directory \HDL_Library\Lab6\sys_gen_ip\ip\drivers\lab6_1_v1_2\src and view the driver files.

    The driver files for the AXI4-Lite interface are automatically created by Model Composer when it saves a design in IP Catalog format.



  11. Open file lab6_1_hw.h to review which addresses the ports in the AXI4-Lite interface were automatically assigned.

  12. Open file lab6_1.c to review the C code for the driver functions. These are used to read and write to the AXI4-Lite registers and can be incorporated into your C program running on the Zynq®-7000 CPU. The function to write to the decrypt register is shown in the following figure.

    The driver files are automatically included when the Model Composer design is added to the IP Catalog. The procedure for adding a Model Composer design to the IP Catalog is detailed in Lab 5: Using AXI Interfaces and IP Integrator. In the next step, you will implement the design.