Step 1: Review the AXI Interfaces - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)

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2021.1 English
In this step you review how AXI interfaces are defined and created.
  1. Invoke Vitis Model Composer and use the Current Folder browser to change the directory to \HDL_Library\Lab5.
  2. Type open Lab5_1.slx in the Command Window.

    This opens the design shown in the following figure.

    This design uses a number of AXI interfaces. You will review these shortly.

    • Using AXI interfaces allows a design exported to the Vivado IP catalog to be efficiently integrated into a larger system using IP integrator.
    • It is not a requirement for designs exported to the IP catalog to use AXI interfaces.

    This design uses the following AXI interfaces:

    • An AXI4-Stream interface is used for ports s_axis_source_*. All Gateway In and Out signals are prefixed with the same name (s_axis_source_), ensuring they are grouped into the same interface. The suffixes for all ports are valid AXI4-Stream interface signal names (tready, tvalid, tlast and tdata).
    • An AXI4-Stream interface is used for ports m_axis_dout_*.
    • An AXI4-Lite interface is used for the remaining ports. You can confirm this using the following steps:
  3. Double-click Gateway In instance decrypt (or any of reset, Keys[63:32], Keys[31:0], or parity_err).
  4. In the Properties Editor select the Implementation tab.
  5. Confirm the Interface is specified as AXI4-Lite in the Interface options.
  6. Click OK to exit the Properties Editor.

    Details on simulating the design are provided in the canvas notes. For this exercise, you will concentrate on exporting the design to the Vivado IP catalog and use the IP in an existing design.