Part 1: Designing with Floating-Point Data Types - 2021.1 English

Vitis Model Composer Tutorial: (UG1498)

Document ID
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2021.1 English
In this part you will review a design implemented with floating-point data types.
  1. At the command prompt, type open Lab1_4_1.slx.

    This opens the Simulink design shown in the following figure. This design is similar to the design used in Lab 1_1, however this time the design is using float data types and the filter is implemented in sub-system FIR.

    First, you will review the attributes of the design, then simulate the design to review the performance, and finally synthesize the design.

    In the previous figure, both the input and output of instance FIR are of type double.
  2. In the MATLAB Command Window enter:
    MyCoeffs = xlfda_numerator('FDATool')
  3. Double-click the instance FIR to open the sub-system.
  4. Double-click the instance Constant1 to open the Properties Editor.

    This shows the Constant value is defined by MyCoeffs(1).

  5. Close the Constant1 Properties editor.
  6. Return to the top-level design using the toolbar button Up To Parent , or click the tab labeled Lab1_4_1.

    The design is summing two sine waves, both of which are 9 MHz. The input gateway to the Model Composer must therefore sample at a rate of at least 18 MHz.

  7. Double-click the Gateway In1 instance to open the Properties Editor and confirm the input is sampling the data at a rate of 20 MHz (a Sample period of 1/20e6).
  8. Close the Gateway In Properties editor.
  9. Click the Run simulation button to simulate the design.

    The results shown in the following figure show the Model Composer HDL blockset produces results which are very close to the ideal case, shown in the center. The results are not identical because the Model Composer design must sample the continuous input waveform into discrete time values.

    The final step is to synthesize this design into hardware.

  10. Double-click the System Generator token to open the Properties Editor.
  11. On the Compilation tab, make sure the Compilation target is IP Catalog.
  12. On the Clocking tab, under Perform analysis select Post Synthesis and from Analyzer type menu select Resource. This option gives the resource utilization details after completion.
  13. Click Generate to compile the design into a hardware description. After completion, it generates the resource utilization in Resource Analyzer window as shown in the following figure.

  14. Click OK to dismiss the Compilation status dialog box.
  15. Click OK to dismiss the System Generator token.

    You implemented this same filter in Step 1 using fixed-point data types. When compared to the synthesis results from that implementation – the initial results from Step are shown in the following figure and you can see this current version of the design is using a large amount of registers (FF), LUTs, and DSP48 (DSP) resources (Xilinx dedicated multiplier/add units).

    Maintaining the full accuracy of floating-point types is an ideal implementation but implementing full floating-point accuracy requires a significant amount of hardware.

    For this particular design, the entire range of the floating-point types is not required. The design is using considerably more resources than what is required. In the next part, you will learn how to compare designs with different data types inside the Simulink environment.

  16. Exit the Vivado Design Suite.
  17. Exit the Lab1_4_1.slx Simulink worksheet.