PL Interface Tile Capabilities - 2020.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
Release Date
2020.2 English

The AI Engine clock is set to run at minimum of 1 GHz or higher based on the device speed grade. The default width of a stream channel is 32 bits. Because this frequency is higher than the PL clock frequency, it is always necessary to perform a clock domain crossing to the PL region, for example, to either one-half or a quarter of the AI Engine clock frequency.

Recommended: Though not required, Xilinx recommends running the PL kernel with a frequency where the AI Engine frequency is an integer multiple of the PL kernel frequency.

For C++ HLS PL kernels, choose a reasonable target frequency depending on the complexity of the algorithm implemented. adf::pl_frequency constraints can be used to constrain each PL kernel in a graph. For example, adf::pl_frequency(<PL_KERNEL>) = freq; construct can be used in the AI Engine compiler and the --hls.clock option can be used in the Vitis compiler when compiling HLS C/C++ into Xilinx object (XO) files.