PL Kernels - 2020.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
Release Date
2020.2 English

Kernels implemented in the programmable logic (PL) region of the Versal device can be integrated into an AI Engine graph application, or can work alongside it. PL kernels can take the form of HLS kernels, written in C/C++ or OpenCL, or RTL kernels packaged in the Vivado Design Suite. These kernels must be separately compiled to produce the Xilinx object files (XO) used in integrating the system design on the target platform.

HLS kernels, written in C/C++ or OpenCL, can be written and compiled from within the Vitis HLS tool directly, or as part of the Vitis application acceleration development flow.

For information on creating and building RTL kernels, see RTL Kernels in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).