Vitis Tools Template Examples - 2020.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
Release Date
2020.2 English

The last page of the New Application Project wizard in the Vitis IDE (shown in the following figure), displays a list of template applications that can be used for your design. Selecting a template creates a sample AI Engine graph application, and imports the necessary source code to let you build and examine different elements of the application simulation design.

Figure 1. AI Engine Application Templates

The template projects illustrate the basic features of AI Engine programming. You can study these templates, use them as a starting point for your own projects, or mix and match the features to create your own complex computation graphs. The following table describes some of the template applications.

Table 1. Template Application Examples
Template Name Description Further Information
AI Engine, PL and PS System Design This design demonstrates integrating the AI Engine array with the Programmable Logic and the Processing System in a system. It performs hardware co-simulation and hardware implementation. Integrating the Application Using the Vitis Tools Flow
Async_buffer A graph to demonstrate asynchronous window APIs. Asynchronous Window Access
Async_rtp_control_iterative A graph to demonstrate simple use of asynchronous RTP update and run with specified test iterations Graph Execution Control
C++ template example An example demonstrating C++ templated data types and state encapsulation C++ Template Support
GMIO_bandwidth A graph to demonstrate GMIO performance profiling. GMIO Attributes
MappingPlacement A templated graph with relocatable mapping and location constraints for kernels Location Constraints
ShimConstraints A graph to demonstrate physical channel allocation constraints on the AI Engine to PL interface boundary. AI Engine/Programmable Logic Integration
Simple A simple 2-kernel graph with window based data communication Window-based Access
Simple_128_bit_interface A graph to demonstrate 128-bit interface between the AI Engine and PL PLIO Attributes
Simple_64_bit_interface A graph to demonstrate 64-bit interface between the AI Engine and PL PLIO Attributes
Simple_bypass_test A graph demonstrating the use of bypass for kernels Kernel Bypass
Simple_chained A simple 2-kernel graph with triggered array parameter communication between the kernels Chained Updates Between AI Engine Kernels
Simple_margin A graph demonstrating the use of margin in windows (overlapping windows) Window-based Access
Simple_packet_split_merge A graph to demonstrate simple split and merge of packet stream data. Explicit Packet Switching
Simple_param A simple 1-kernel graph with scalar parameter update using external trigger Specifying Run-Time Data Parameters
Simple_single_buffer_test A graph demonstrating single buffer constraint on connections Buffer Allocation Control
Single_node_graph A simple single node graph with demonstration window (single buffer and double buffer), stream and RTP array connections. Single Kernel Development
StreamSwitchFIFO A graph to demonstrate use of stream switch FIFO to avoid deadlocks with reconvergent streams Stream FIFO Depth