PL-to-PL Connections - 2020.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

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2020.2 English

Multiple PL kernels can be defined inside the graph, with stream connections between the PL kernels. But only PL kernel streams with the same width can be connected for the AI Engine simulator.

However, the Vitis compiler can automatically insert a data-width converter and clock-domain crossing IP between the connections of PL kernels outside the graph to resolve any mismatch in bit width or frequency. Taking these facts into consideration, you must carefully choose which PL kernels are inside or outside the graph.